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| author | Peng Fan <peng.fan@nxp.com> | 2016-01-29 10:06:34 +0800 |
|---|---|---|
| committer | guoyin.chen <guoyin.chen@freescale.com> | 2016-03-04 15:35:56 +0800 |
| commit | 38cf99a6c23dc12b88616d4b8505d71054935a1c (patch) | |
| tree | 6b96db4575b8861279ad04a38f4582e80948a395 /board/freescale/mx7dsabresd | |
| parent | de732af53dab8252353d5d4aeafcc5a8df99968d (diff) | |
| download | u-boot-imx-38cf99a6c23dc12b88616d4b8505d71054935a1c.zip u-boot-imx-38cf99a6c23dc12b88616d4b8505d71054935a1c.tar.gz u-boot-imx-38cf99a6c23dc12b88616d4b8505d71054935a1c.tar.bz2 | |
MLK-12346 imx: mx7d: switch to use DRAM_PLL, but not DRAM_ALT_CLK_ROOT
To simplify kernel clock management, we switch to use DRAM_PLL for
DRAM controller and DDR PHY, but not use DRAM_ALT_CLK_ROOT.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'board/freescale/mx7dsabresd')
| -rw-r--r-- | board/freescale/mx7dsabresd/imximage.cfg | 7 | ||||
| -rw-r--r-- | board/freescale/mx7dsabresd/plugin.S | 27 |
2 files changed, 26 insertions, 8 deletions
diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg index 2ffc838..db4c939 100644 --- a/board/freescale/mx7dsabresd/imximage.cfg +++ b/board/freescale/mx7dsabresd/imximage.cfg @@ -50,8 +50,11 @@ CSF CONFIG_CSF_SIZE * value value to be stored in the register */ -DATA 4 0x3038a080 0x15000000 -DATA 4 0x30389880 0x01000000 +DATA 4 0x30360070 0x00703021 +DATA 4 0x30360090 0x0 +DATA 4 0x30360070 0x00603021 +CHECK_BITS_SET 4 0x30360070 0x80000000 +DATA 4 0x30389880 0x1 DATA 4 0x30340004 0x4F400005 diff --git a/board/freescale/mx7dsabresd/plugin.S b/board/freescale/mx7dsabresd/plugin.S index 796716f..5c4bc86 100644 --- a/board/freescale/mx7dsabresd/plugin.S +++ b/board/freescale/mx7dsabresd/plugin.S @@ -45,13 +45,28 @@ TUNE_END: bne FREQ_DEFAULT_533 /* Change to 400Mhz for TO1.1 */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =0x70 + ldr r2, =0x00703021 + str r2, [r0, r1] + ldr r1, =0x90 + ldr r2, =0x0 + str r2, [r0, r1] + ldr r1, =0x70 + ldr r2, =0x00603021 + str r2, [r0, r1] + + ldr r3, =0x80000000 +wait_lock: + ldr r2, [r0, r1] + and r2, r3 + cmp r2, r3 + bne wait_lock + ldr r0, =CCM_BASE_ADDR - ldr r1, =0x15000000 - ldr r2, =0xa080 - str r1, [r0, r2] - ldr r1, =0x01000000 - ldr r2, =0x9880 - str r1, [r0, r2] + ldr r1, =0x9880 + ldr r2, =0x1 + str r2, [r0, r1] FREQ_DEFAULT_533: .endm |