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author | Ye Li <ye.li@nxp.com> | 2016-12-07 11:37:05 +0800 |
---|---|---|
committer | Ye Li <ye.li@nxp.com> | 2017-04-05 19:48:57 +0800 |
commit | b4db09bc0fc96e7c7461afade6346e0700ad582f (patch) | |
tree | 0c914c8f4aedcf069e974b4c60ef8aff7c9d38bb /board/freescale/mx7dsabresd | |
parent | d78d25cfb4cf64507e5839e525ce82e0897a609c (diff) | |
download | u-boot-imx-b4db09bc0fc96e7c7461afade6346e0700ad582f.zip u-boot-imx-b4db09bc0fc96e7c7461afade6346e0700ad582f.tar.gz u-boot-imx-b4db09bc0fc96e7c7461afade6346e0700ad582f.tar.bz2 |
MLK-13586-2 mx7d_arm2/sabresd: Update ddr3 script to V2.0 for Bank interleave
To improve the performance, enable the bank interleave for DDR3. Update
the DDR3 settings to new script IMX7D_DDR3_533MHz_1GB_32bit_V2.0.ds
Changes:
1. Enable bank interleave
2. Improve the drive strength for non-TO1.1 chips.
3. Updates ZQ_CON0 settings.
4. For 19x19 DDR3 ARM2 and 12x12 DDR3 ARM2, they are using old version scripts which
were not upgrade with SABRESD script. According to DDR owner suggestion, to use same version
script for all of them.
File:
http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1
Test:
Passed stress test on one TO1.2 SABRESD, one TO1.1 SABRESD and one TO1.0 SABRESD.
Passed stress test on one 12x12 ddr3 ARM2.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 62e73b45c53e3302d869c373da72699199b90648)
Diffstat (limited to 'board/freescale/mx7dsabresd')
-rw-r--r-- | board/freescale/mx7dsabresd/imximage.cfg | 10 | ||||
-rw-r--r-- | board/freescale/mx7dsabresd/imximage_TO_1_1.cfg | 8 | ||||
-rw-r--r-- | board/freescale/mx7dsabresd/plugin.S | 12 |
3 files changed, 15 insertions, 15 deletions
diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg index 4dca2d3..a982eac 100644 --- a/board/freescale/mx7dsabresd/imximage.cfg +++ b/board/freescale/mx7dsabresd/imximage.cfg @@ -76,9 +76,10 @@ DATA 4 0x307a0184 0x02000100 DATA 4 0x307a0190 0x02098204 DATA 4 0x307a0194 0x00030303 DATA 4 0x307a0200 0x00000016 -DATA 4 0x307a0204 0x00171717 -DATA 4 0x307a0214 0x04040404 -DATA 4 0x307a0218 0x0f040404 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 DATA 4 0x307a0240 0x06000604 DATA 4 0x307a0244 0x00000001 DATA 4 0x30391000 0x00000000 @@ -86,7 +87,7 @@ DATA 4 0x30790000 0x17420f40 DATA 4 0x30790004 0x10210100 DATA 4 0x30790010 0x00060807 DATA 4 0x307900b0 0x1010007e -DATA 4 0x3079009c 0x00000d6e +DATA 4 0x3079009c 0x00000b24 DATA 4 0x30790020 0x08080808 DATA 4 0x30790030 0x08080808 DATA 4 0x30790050 0x01000010 @@ -98,7 +99,6 @@ DATA 4 0x307900c0 0x0e447306 CHECK_BITS_SET 4 0x307900c4 0x1 -DATA 4 0x307900c0 0x0e447304 DATA 4 0x307900c0 0x0e407304 diff --git a/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg b/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg index 66cc99c..48413de 100644 --- a/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg +++ b/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg @@ -81,9 +81,10 @@ DATA 4 0x307a0184 0x02000100 DATA 4 0x307a0190 0x02098204 DATA 4 0x307a0194 0x00030303 DATA 4 0x307a0200 0x00000016 -DATA 4 0x307a0204 0x00171717 -DATA 4 0x307a0214 0x04040404 -DATA 4 0x307a0218 0x0f040404 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 DATA 4 0x307a0240 0x06000604 DATA 4 0x307a0244 0x00000001 DATA 4 0x30391000 0x00000000 @@ -108,7 +109,6 @@ DATA 4 0x307900c0 0x0e447306 CHECK_BITS_SET 4 0x307900c4 0x1 -DATA 4 0x307900c0 0x0e447304 DATA 4 0x307900c0 0x0e407304 diff --git a/board/freescale/mx7dsabresd/plugin.S b/board/freescale/mx7dsabresd/plugin.S index 2dce883..75033f7 100644 --- a/board/freescale/mx7dsabresd/plugin.S +++ b/board/freescale/mx7dsabresd/plugin.S @@ -31,7 +31,7 @@ NO_DELAY: /*TO 1.0*/ - ldr r1, =0x00000d6e + ldr r1, =0x00000b24 str r1, [r0, #0x9c] TUNE_END: @@ -140,11 +140,13 @@ FREQ_DEFAULT_533: ldr r1, =0x00000016 str r1, [r0, #0x200] - ldr r1, =0x00171717 + ldr r1, =0x00080808 str r1, [r0, #0x204] - ldr r1, =0x04040404 + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x07070707 str r1, [r0, #0x214] - ldr r1, =0x0f040404 + ldr r1, =0x0f070707 str r1, [r0, #0x218] ldr r1, =0x06000604 @@ -186,8 +188,6 @@ wait_zq: tst r1, #0x1 beq wait_zq - ldr r1, =0x0e447304 - str r1, [r0, #0xc0] ldr r1, =0x0e407304 str r1, [r0, #0xc0] |