diff options
| author | Ye Li <ye.li@nxp.com> | 2016-12-07 11:37:05 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 19:48:57 +0800 |
| commit | b4db09bc0fc96e7c7461afade6346e0700ad582f (patch) | |
| tree | 0c914c8f4aedcf069e974b4c60ef8aff7c9d38bb /board/freescale/mx7dsabresd/plugin.S | |
| parent | d78d25cfb4cf64507e5839e525ce82e0897a609c (diff) | |
| download | u-boot-imx-b4db09bc0fc96e7c7461afade6346e0700ad582f.zip u-boot-imx-b4db09bc0fc96e7c7461afade6346e0700ad582f.tar.gz u-boot-imx-b4db09bc0fc96e7c7461afade6346e0700ad582f.tar.bz2 | |
MLK-13586-2 mx7d_arm2/sabresd: Update ddr3 script to V2.0 for Bank interleave
To improve the performance, enable the bank interleave for DDR3. Update
the DDR3 settings to new script IMX7D_DDR3_533MHz_1GB_32bit_V2.0.ds
Changes:
1. Enable bank interleave
2. Improve the drive strength for non-TO1.1 chips.
3. Updates ZQ_CON0 settings.
4. For 19x19 DDR3 ARM2 and 12x12 DDR3 ARM2, they are using old version scripts which
were not upgrade with SABRESD script. According to DDR owner suggestion, to use same version
script for all of them.
File:
http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1
Test:
Passed stress test on one TO1.2 SABRESD, one TO1.1 SABRESD and one TO1.0 SABRESD.
Passed stress test on one 12x12 ddr3 ARM2.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 62e73b45c53e3302d869c373da72699199b90648)
Diffstat (limited to 'board/freescale/mx7dsabresd/plugin.S')
| -rw-r--r-- | board/freescale/mx7dsabresd/plugin.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/board/freescale/mx7dsabresd/plugin.S b/board/freescale/mx7dsabresd/plugin.S index 2dce883..75033f7 100644 --- a/board/freescale/mx7dsabresd/plugin.S +++ b/board/freescale/mx7dsabresd/plugin.S @@ -31,7 +31,7 @@ NO_DELAY: /*TO 1.0*/ - ldr r1, =0x00000d6e + ldr r1, =0x00000b24 str r1, [r0, #0x9c] TUNE_END: @@ -140,11 +140,13 @@ FREQ_DEFAULT_533: ldr r1, =0x00000016 str r1, [r0, #0x200] - ldr r1, =0x00171717 + ldr r1, =0x00080808 str r1, [r0, #0x204] - ldr r1, =0x04040404 + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x07070707 str r1, [r0, #0x214] - ldr r1, =0x0f040404 + ldr r1, =0x0f070707 str r1, [r0, #0x218] ldr r1, =0x06000604 @@ -186,8 +188,6 @@ wait_zq: tst r1, #0x1 beq wait_zq - ldr r1, =0x0e447304 - str r1, [r0, #0xc0] ldr r1, =0x0e407304 str r1, [r0, #0xc0] |