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| author | Ye.Li <B37916@freescale.com> | 2015-03-03 22:46:54 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-04-29 14:58:50 +0800 |
| commit | 7e755125b567174ccf2aa19e27667d8d1f8a0d24 (patch) | |
| tree | 7fafa8ba44a189ae5a429ad44b6b75e79e07060b /board/freescale/mx7d_19x19_ddr3_arm2 | |
| parent | 4b945370c326d74058fe30b473707915023e8bbb (diff) | |
| download | u-boot-imx-7e755125b567174ccf2aa19e27667d8d1f8a0d24.zip u-boot-imx-7e755125b567174ccf2aa19e27667d8d1f8a0d24.tar.gz u-boot-imx-7e755125b567174ccf2aa19e27667d8d1f8a0d24.tar.bz2 | |
MLK-10361 imx: mx7d arm2: Change to use WDOG_B reset
The default u-boot reset is a internal WDOG reset (warm reset on i.MX6) which
does not have power and DDR reset. So the peripherals and DDR may meet problem.
When using the internal WDOG reset on i.MX7D ARM2 boards,
we meets two DDR issues:
1. On 12x12 ARM2, sometimes the system may hang in DCD because the DDRC Operating Mode
does not become to normal.
2. On 19x19 ARM2, the reset always brings system to USB download because the
DDR3 turns to unstable.
On the i.MX7D ARM2 board, the WDOG_B signal connects to POR_B or PMIC_PWRON. This gives
a chance to use a stronger reset. So in this patch, we set the IOMUX for WDOG_B pin and
enable WDOG_B signal output in WDOG WCR register.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 1192501c1fcf3b266eb22639a6bc93ac7c03b367)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'board/freescale/mx7d_19x19_ddr3_arm2')
| -rw-r--r-- | board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c b/board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c index b76760c..5c108f2 100644 --- a/board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c +++ b/board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c @@ -559,8 +559,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); - /* Reset peripherals */ imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads)); @@ -653,6 +651,10 @@ int board_late_init(void) board_late_mmc_init(); #endif + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + return 0; } |