MLK-13586-2 mx7d_arm2/sabresd: Update ddr3 script to V2.0 for Bank interleave

To improve the performance, enable the bank interleave for DDR3. Update
the DDR3 settings to new script IMX7D_DDR3_533MHz_1GB_32bit_V2.0.ds

Changes:
    1. Enable bank interleave
    2. Improve the drive strength for non-TO1.1 chips.
    3. Updates ZQ_CON0 settings.
    4. For 19x19 DDR3 ARM2 and 12x12 DDR3 ARM2, they are using old version scripts which
       were not upgrade with SABRESD script. According to DDR owner suggestion, to use same version
       script for all of them.

File:
    http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1

Test:
    Passed stress test on one TO1.2 SABRESD, one TO1.1 SABRESD and one TO1.0 SABRESD.
    Passed stress test on one 12x12 ddr3 ARM2.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 62e73b45c53e3302d869c373da72699199b90648)

1 files changed, 26 insertions, 16 deletions

diff --git a/board/freescale/mx7d_19x19_ddr3_arm2/plugin.S b/board/freescale/mx7d_19x19_ddr3_arm2/plugin.S
index 39d53d6..c2ca47a 100644
--- a/board/freescale/mx7d_19x19_ddr3_arm2/plugin.S
+++ b/board/freescale/mx7d_19x19_ddr3_arm2/plugin.S
@@ -31,7 +31,7 @@
 
 NO_DELAY:
 	/*TO 1.0*/
-	ldr r1, =0x00000d6e
+	ldr r1, =0x00000b24
 	str r1, [r0, #0x9c]
 
 TUNE_END:
@@ -79,13 +79,19 @@ FREQ_DEFAULT_533:
 	ldr r1, =0x4f400005
 	str r1, [r0, #0x4]
 
+	/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
+	ldr r0, =ANATOP_BASE_ADDR
+	ldr r1, =(0x1 << 30)
+	str r1, [r0, #0x388]
+	str r1, [r0, #0x384]
+
 	ldr r0, =SRC_BASE_ADDR
 	ldr r1, =0x2
 	ldr r2, =0x1000
 	str r1, [r0, r2]
 
 	ldr r0, =DDRC_IPS_BASE_ADDR
-	ldr r1, =0x03040001
+	ldr r1, =0x01040001
 	str r1, [r0]
 	ldr r1, =0x80400003
 	str r1, [r0, #0x1a0]
@@ -93,38 +99,40 @@ FREQ_DEFAULT_533:
 	str r1, [r0, #0x1a4]
 	ldr r1, =0x80100004
 	str r1, [r0, #0x1a8]
-	ldr r1, =0x0040005e
+	ldr r1, =0x00400046
 	str r1, [r0, #0x64]
 	ldr r1, =0x1
 	str r1, [r0, #0x490]
 	ldr r1, =0x00020001
 	str r1, [r0, #0xd0]
-	ldr r1, =0x00010000
+	ldr r1, =0x00690000
 	str r1, [r0, #0xd4]
 	ldr r1, =0x09300004
 	str r1, [r0, #0xdc]
 	ldr r1, =0x04080000
 	str r1, [r0, #0xe0]
-	ldr r1, =0x00090004
+	ldr r1, =0x00100004
 	str r1, [r0, #0xe4]
 	ldr r1, =0x33f
 	str r1, [r0, #0xf4]
-	ldr r1, =0x0908120a
+	ldr r1, =0x09081109
 	str r1, [r0, #0x100]
-	ldr r1, =0x0002020e
+	ldr r1, =0x0007020d
 	str r1, [r0, #0x104]
 	ldr r1, =0x03040407
 	str r1, [r0, #0x108]
 	ldr r1, =0x00002006
 	str r1, [r0, #0x10c]
-	ldr r1, =0x04020204
+	ldr r1, =0x04020205
 	str r1, [r0, #0x110]
 	ldr r1, =0x03030202
 	str r1, [r0, #0x114]
-	ldr r1, =0x03030803
+	ldr r1, =0x00000803
 	str r1, [r0, #0x120]
 	ldr r1, =0x00800020
 	str r1, [r0, #0x180]
+	ldr r1, =0x02000100
+	str r1, [r0, #0x184]
 	ldr r1, =0x02098204
 	str r1, [r0, #0x190]
 	ldr r1, =0x00030303
@@ -132,16 +140,18 @@ FREQ_DEFAULT_533:
 
 	ldr r1, =0x00000016
 	str r1, [r0, #0x200]
-	ldr r1, =0x00171717
+	ldr r1, =0x00080808
 	str r1, [r0, #0x204]
-	ldr r1, =0x04040404
+	ldr r1, =0x00000f0f
+	str r1, [r0, #0x210]
+	ldr r1, =0x07070707
 	str r1, [r0, #0x214]
-	ldr r1, =0x00040404
+	ldr r1, =0x0f070707
 	str r1, [r0, #0x218]
 
-	ldr r1, =0x06000601
+	ldr r1, =0x06000604
 	str r1, [r0, #0x240]
-	ldr r1, =0x00001323
+	ldr r1, =0x00000001
 	str r1, [r0, #0x244]
 
 	ldr r0, =SRC_BASE_ADDR
@@ -156,6 +166,8 @@ FREQ_DEFAULT_533:
 	str r1, [r0, #0x4]
 	ldr r1, =0x00060807
 	str r1, [r0, #0x10]
+	ldr r1, =0x1010007e
+	str r1, [r0, #0xb0]
 	imx7d_ddrphy_latency_setting
 	ldr r1, =0x08080808
 	str r1, [r0, #0x20]
@@ -176,8 +188,6 @@ wait_zq:
 	tst r1, #0x1
 	beq wait_zq
 
-	ldr r1, =0x0e447304
-	str r1, [r0, #0xc0]
 	ldr r1, =0x0e407304
 	str r1, [r0, #0xc0]