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author | Ye.Li <B37916@freescale.com> | 2015-02-02 12:53:23 +0800 |
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committer | Peng Fan <Peng.Fan@freescale.com> | 2015-04-29 14:56:33 +0800 |
commit | 122e17706547c5a72b84332c8f1dc47914ff6279 (patch) | |
tree | d5e1accafd07a4f23d0a5a703efec2965fcd79bd /board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S | |
parent | b81a3cbc857c440098e970c4bff1abd710cfbdd7 (diff) | |
download | u-boot-imx-122e17706547c5a72b84332c8f1dc47914ff6279.zip u-boot-imx-122e17706547c5a72b84332c8f1dc47914ff6279.tar.gz u-boot-imx-122e17706547c5a72b84332c8f1dc47914ff6279.tar.bz2 |
MLK-10191-3 imx: mx7: Add support for i.MX7D 12x12 LPDDR3 ARM2 board
Add BSP codes, configuration head file and build target for
12x12 LPDDR3 ARM2 board with basic functions:
ENET, I2C, SD/eMMC/MMC, USB, LCD Splash screen, QSPI, ECSPI,
pfuze3000 PMIC.
Note: pmic and video is still not upstream way
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit ac0d51ef07fdec880e6da318c08d521506640efa)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
boards.cfg
Diffstat (limited to 'board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S')
-rw-r--r-- | board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S | 162 |
1 files changed, 162 insertions, 0 deletions
diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S new file mode 100644 index 0000000..cdc6d47 --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> + +/* DDR script */ +.macro imx7d_12x12_lpddr3_arm2_setting + /* down pll_ddr to 800M */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =0x00603021 + str r1, [r0, #0x70] +wait_freq: + ldr r1, [r0, #0x70] + tst r1, #0x80000000 + beq wait_freq + + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x03040008 + str r1, [r0] + ldr r1, =0x00210038 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00350001 + str r1, [r0, #0xd0] + ldr r1, =0x00c3000a + str r1, [r0, #0xdc] + ldr r1, =0x00020000 + str r1, [r0, #0xe0] + ldr r1, =0x00110006 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x0a0e110b + str r1, [r0, #0x100] + ldr r1, =0x00020211 + str r1, [r0, #0x104] + ldr r1, =0x03060707 + str r1, [r0, #0x108] + ldr r1, =0x00a0500c + str r1, [r0, #0x10c] + ldr r1, =0x05020307 + str r1, [r0, #0x110] + ldr r1, =0x02020404 + str r1, [r0, #0x114] + ldr r1, =0x02020003 + str r1, [r0, #0x118] + ldr r1, =0x00000202 + str r1, [r0, #0x11c] + ldr r1, =0x00600018 + str r1, [r0, #0x180] + ldr r1, =0x00e00100 + str r1, [r0, #0x184] + ldr r1, =0x02098205 + str r1, [r0, #0x190] + ldr r1, =0x00060303 + str r1, [r0, #0x194] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00001020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00171717 + str r1, [r0, #0x204] + ldr r1, =0x05050505 + str r1, [r0, #0x214] + ldr r1, =0x00050505 + str r1, [r0, #0x218] + + ldr r1, =0x06000601 + str r1, [r0, #0x240] + mov r1, #0x0 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17421e40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00010000 + str r1, [r0, #0x8] + ldr r1, =0x0007080c + str r1, [r0, #0x10] + ldr r1, =0x01010000 + str r1, [r0, #0x1c] + ldr r1, =0x0db60db6 + str r1, [r0, #0x9c] + ldr r1, =0x0000000f + str r1, [r0, #0x18] + ldr r1, =0x0f407304 + str r1, [r0, #0xc0] + ldr r1, =0x0f447304 + str r1, [r0, #0xc0] + ldr r1, =0x0f447306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0f407304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x01000018 + str r1, [r0, #0x50] + ldr r1, =0x00000018 + str r1, [r0, #0x50] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting + imx7d_12x12_lpddr3_arm2_setting +.endm + +/* include the common plugin code here */ +#include <asm/arch/mx7_plugin.S> |