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authorYe.Li <B37916@freescale.com>2015-02-02 12:53:23 +0800
committerPeng Fan <Peng.Fan@freescale.com>2015-04-29 14:56:33 +0800
commit122e17706547c5a72b84332c8f1dc47914ff6279 (patch)
treed5e1accafd07a4f23d0a5a703efec2965fcd79bd /board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg
parentb81a3cbc857c440098e970c4bff1abd710cfbdd7 (diff)
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MLK-10191-3 imx: mx7: Add support for i.MX7D 12x12 LPDDR3 ARM2 board
Add BSP codes, configuration head file and build target for 12x12 LPDDR3 ARM2 board with basic functions: ENET, I2C, SD/eMMC/MMC, USB, LCD Splash screen, QSPI, ECSPI, pfuze3000 PMIC. Note: pmic and video is still not upstream way Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit ac0d51ef07fdec880e6da318c08d521506640efa) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Conflicts: boards.cfg
Diffstat (limited to 'board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg')
-rw-r--r--board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg113
1 files changed, 113 insertions, 0 deletions
diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg
new file mode 100644
index 0000000..2536309
--- /dev/null
+++ b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_SYS_BOOT_QSPI
+BOOT_FROM qspi
+#elif defined(CONFIG_SYS_BOOT_EIMNOR)
+BOOT_FROM nor
+#else
+BOOT_FROM sd
+#endif
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx7d_12x12_lpddr3_arm2/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF 0x2000
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+
+DATA 4 0x30360070 0x00603021
+CHECK_DATA 4 0x30360070 0x80000000
+
+DATA 4 0x30340004 0x4F400005
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x03040008
+DATA 4 0x307a0064 0x00210038
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00350001
+DATA 4 0x307a00dc 0x00c3000a
+DATA 4 0x307a00e0 0x00020000
+DATA 4 0x307a00e4 0x00110006
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x0a0e110b
+DATA 4 0x307a0104 0x00020211
+DATA 4 0x307a0108 0x03060707
+DATA 4 0x307a010c 0x00a0500c
+DATA 4 0x307a0110 0x05020307
+DATA 4 0x307a0114 0x02020404
+DATA 4 0x307a0118 0x02020003
+DATA 4 0x307a011c 0x00000202
+DATA 4 0x307a0180 0x00600018
+DATA 4 0x307a0184 0x00e00100
+DATA 4 0x307a0190 0x02098205
+DATA 4 0x307a0194 0x00060303
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00001020
+DATA 4 0x307a01a8 0x80100004
+
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00171717
+DATA 4 0x307a0214 0x05050505
+DATA 4 0x307a0218 0x00050505
+
+DATA 4 0x307a0240 0x06000601
+DATA 4 0x307a0244 0x00000000
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17421e40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790008 0x00010000
+DATA 4 0x30790010 0x0007080c
+DATA 4 0x3079001C 0x01010000
+DATA 4 0x3079009c 0x0db60db6
+DATA 4 0x30790018 0x0000000f
+DATA 4 0x307900c0 0x0f407304
+DATA 4 0x307900c0 0x0f447304
+DATA 4 0x307900c0 0x0f447306
+
+CHECK_DATA 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0f407304
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790050 0x01000018
+DATA 4 0x30790050 0x00000018
+
+CHECK_DATA 4 0x307a0004 0x1
+#endif