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| author | Ye Li <ye.li@nxp.com> | 2016-12-07 11:37:05 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 19:48:57 +0800 |
| commit | b4db09bc0fc96e7c7461afade6346e0700ad582f (patch) | |
| tree | 0c914c8f4aedcf069e974b4c60ef8aff7c9d38bb /board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg | |
| parent | d78d25cfb4cf64507e5839e525ce82e0897a609c (diff) | |
| download | u-boot-imx-b4db09bc0fc96e7c7461afade6346e0700ad582f.zip u-boot-imx-b4db09bc0fc96e7c7461afade6346e0700ad582f.tar.gz u-boot-imx-b4db09bc0fc96e7c7461afade6346e0700ad582f.tar.bz2 | |
MLK-13586-2 mx7d_arm2/sabresd: Update ddr3 script to V2.0 for Bank interleave
To improve the performance, enable the bank interleave for DDR3. Update
the DDR3 settings to new script IMX7D_DDR3_533MHz_1GB_32bit_V2.0.ds
Changes:
1. Enable bank interleave
2. Improve the drive strength for non-TO1.1 chips.
3. Updates ZQ_CON0 settings.
4. For 19x19 DDR3 ARM2 and 12x12 DDR3 ARM2, they are using old version scripts which
were not upgrade with SABRESD script. According to DDR owner suggestion, to use same version
script for all of them.
File:
http://compass.freescale.net/livelink/livelink?func=ll&objid=233861153&objAction=browse&sort=name&viewType=1
Test:
Passed stress test on one TO1.2 SABRESD, one TO1.1 SABRESD and one TO1.0 SABRESD.
Passed stress test on one 12x12 ddr3 ARM2.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 62e73b45c53e3302d869c373da72699199b90648)
Diffstat (limited to 'board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg')
| -rw-r--r-- | board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg | 37 |
1 files changed, 22 insertions, 15 deletions
diff --git a/board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg b/board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg index 62bb99d..766b9ca 100644 --- a/board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg +++ b/board/freescale/mx7d_12x12_ddr3_arm2/imximage_TO_1_1.cfg @@ -52,40 +52,46 @@ CHECK_BITS_SET 4 0x30360070 0x80000000 DATA 4 0x30389880 0x1 DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 DATA 4 0x30391000 0x00000002 -DATA 4 0x307a0000 0x03040001 +DATA 4 0x307a0000 0x01040001 DATA 4 0x307a01a0 0x80400003 DATA 4 0x307a01a4 0x00100020 DATA 4 0x307a01a8 0x80100004 -DATA 4 0x307a0064 0x0040005e +DATA 4 0x307a0064 0x00400046 DATA 4 0x307a0490 0x00000001 -DATA 4 0x307a00d0 0x00020001 -DATA 4 0x307a00d4 0x00010000 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 DATA 4 0x307a00dc 0x09300004 DATA 4 0x307a00e0 0x04080000 -DATA 4 0x307a00e4 0x00090004 +DATA 4 0x307a00e4 0x00100004 DATA 4 0x307a00f4 0x0000033f -DATA 4 0x307a0100 0x0908120a -DATA 4 0x307a0104 0x0002020e +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d DATA 4 0x307a0108 0x03040407 DATA 4 0x307a010c 0x00002006 -DATA 4 0x307a0110 0x04020204 +DATA 4 0x307a0110 0x04020205 DATA 4 0x307a0114 0x03030202 -DATA 4 0x307a0120 0x03030803 +DATA 4 0x307a0120 0x00000803 DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 DATA 4 0x307a0190 0x02098204 DATA 4 0x307a0194 0x00030303 DATA 4 0x307a0200 0x00000016 -DATA 4 0x307a0204 0x00171717 -DATA 4 0x307a0214 0x04040404 -DATA 4 0x307a0218 0x00040404 -DATA 4 0x307a0240 0x06000601 -DATA 4 0x307a0244 0x00001323 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 DATA 4 0x30391000 0x00000000 DATA 4 0x30790000 0x17420f40 DATA 4 0x30790004 0x10210100 DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e DATA 4 0x3079009c 0x00000dee DATA 4 0x3079007c 0x18181818 DATA 4 0x30790080 0x18181818 @@ -103,13 +109,14 @@ DATA 4 0x307900c0 0x0e447306 CHECK_BITS_SET 4 0x307900c4 0x1 -DATA 4 0x307900c0 0x0e447304 DATA 4 0x307900c0 0x0e407304 + DATA 4 0x30384130 0x00000000 DATA 4 0x30340020 0x00000178 DATA 4 0x30384130 0x00000002 DATA 4 0x30790018 0x0000000f CHECK_BITS_SET 4 0x307a0004 0x1 + #endif |