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| author | Ye.Li <B37916@freescale.com> | 2015-12-15 11:27:45 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2015-12-17 13:26:22 +0800 |
| commit | 80479ea591a7ae5263ae6930c02884a8b844dcf6 (patch) | |
| tree | ea32343bee9bd0dc41255421a9a1f4c9b74c312a /board/freescale/mx6ul_14x14_evk/imximage.cfg | |
| parent | 68cd8026109b9d912cd71fc764caecd516f434ea (diff) | |
| download | u-boot-imx-80479ea591a7ae5263ae6930c02884a8b844dcf6.zip u-boot-imx-80479ea591a7ae5263ae6930c02884a8b844dcf6.tar.gz u-boot-imx-80479ea591a7ae5263ae6930c02884a8b844dcf6.tar.bz2 | |
MLK-12017 imx: mx6ulevk: Update DDR script for new DDR MT41K256M16TW-107
Current Micron DDR MT41K256M16HA-125 on i.MX6UL will be EOL. Plan is i.MX6UL
will use the new 20nm litho 4Gb DDR3L MT41K256M16TW-107.
Update DDR script of mx6ul evk board for this new DDR, and use it as default.
http://compass.freescale.net/livelink/livelink?func=ll&objId=234910940&objAction=browse&viewType=1
Test result:
Stress test passed.
Meanwhile add build targets below for old DDR support:
mx6ul_14x14_evk_ddr_eol_android_defconfig
mx6ul_14x14_evk_ddr_eol_brillo_defconfig
mx6ul_14x14_evk_ddr_eol_defconfig
mx6ul_14x14_evk_ddr_eol_qspi1_defconfig
Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'board/freescale/mx6ul_14x14_evk/imximage.cfg')
| -rw-r--r-- | board/freescale/mx6ul_14x14_evk/imximage.cfg | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/board/freescale/mx6ul_14x14_evk/imximage.cfg b/board/freescale/mx6ul_14x14_evk/imximage.cfg index 8283673..5d2711f 100644 --- a/board/freescale/mx6ul_14x14_evk/imximage.cfg +++ b/board/freescale/mx6ul_14x14_evk/imximage.cfg @@ -50,6 +50,10 @@ CSF CONFIG_CSF_SIZE * value value to be stored in the register */ +#ifdef CONFIG_DDR3L_MT41K256M16HA + +/* DDR type MT41K256M16HA-125 which is EOL */ + /* Enable all clocks */ DATA 4 0x020c4068 0xffffffff DATA 4 0x020c406c 0xffffffff @@ -111,4 +115,73 @@ DATA 4 0x021B0818 0x00000227 DATA 4 0x021B0004 0x0002552D DATA 4 0x021B0404 0x00011006 DATA 4 0x021B001C 0x00000000 + +#else + +/* New DDR type MT41K256M16TW-107 */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x41570155 +DATA 4 0x021B0848 0x4040474A +DATA 4 0x021B0850 0x40405550 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x23400A38 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif + #endif |