summaryrefslogtreecommitdiff
path: root/board/freescale/mx6sx_19x19_arm2
diff options
context:
space:
mode:
authorYe.Li <B37916@freescale.com>2014-06-12 16:10:49 +0800
committerYe.Li <B37916@freescale.com>2014-06-17 11:14:00 +0800
commit6ab5d58d02675724b24b4936839ff86329b14ddc (patch)
treebfadfabf5b3ed181a1c59892cf3bd1f5ce64b130 /board/freescale/mx6sx_19x19_arm2
parent80f845ada02651e0aaa606eb05372b12a0b7b901 (diff)
downloadu-boot-imx-6ab5d58d02675724b24b4936839ff86329b14ddc.zip
u-boot-imx-6ab5d58d02675724b24b4936839ff86329b14ddc.tar.gz
u-boot-imx-6ab5d58d02675724b24b4936839ff86329b14ddc.tar.bz2
ENGR00315894-63 iMX6SX: Add MX6SX 19x19 LPDDR2 ARM2 board support
Add script "imximage_lpddr2.cfg" for DDR controller settings of LPDDR2. Modify "plugin.S" for LPDDR2. Add build target for 19x19 LPDDR2 ARM2 board. Signed-off-by: Ye.Li <B37916@freescale.com>
Diffstat (limited to 'board/freescale/mx6sx_19x19_arm2')
-rw-r--r--board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg140
-rw-r--r--board/freescale/mx6sx_19x19_arm2/plugin.S141
2 files changed, 281 insertions, 0 deletions
diff --git a/board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg b/board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg
new file mode 100644
index 0000000..3d0deb3
--- /dev/null
+++ b/board/freescale/mx6sx_19x19_arm2/imximage_lpddr2.cfg
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+#ifdef CONFIG_SYS_BOOT_QSPI
+BOOT_FROM qspi
+#elif defined(CONFIG_SYS_BOOT_EIMNOR)
+BOOT_FROM nor
+#else
+BOOT_FROM sd
+#endif
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sx_19x19_arm2/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+SECURE_BOOT
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+DATA 4 0x020e0618 0x00080000
+DATA 4 0x020e05fc 0x00000000
+DATA 4 0x020e032c 0x00000030
+
+DATA 4 0x020e0300 0x00000030
+DATA 4 0x020e02fc 0x00000030
+DATA 4 0x020e05f4 0x00000030
+DATA 4 0x020e0340 0x00000030
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000000
+DATA 4 0x020e0314 0x00000000
+DATA 4 0x020e0614 0x00000030
+
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00003030
+DATA 4 0x020e0334 0x00003030
+DATA 4 0x020e0338 0x00003030
+DATA 4 0x020e033c 0x00003030
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000030
+DATA 4 0x020e0610 0x00000030
+DATA 4 0x020e061c 0x00000030
+DATA 4 0x020e0620 0x00000030
+DATA 4 0x020e02ec 0x00000030
+DATA 4 0x020e02f0 0x00000030
+DATA 4 0x020e02f4 0x00000030
+DATA 4 0x020e02f8 0x00000030
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b085c 0x1b4700c7
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b0890 0x00380000
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b082c 0xf3333333
+DATA 4 0x021b0830 0xf3333333
+DATA 4 0x021b0834 0xf3333333
+DATA 4 0x021b0838 0xf3333333
+DATA 4 0x021b0848 0x3e42424a
+DATA 4 0x021b0850 0x38363832
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x00000000
+DATA 4 0x021b08b8 0x00000800
+
+DATA 4 0x021b000c 0x33374133
+DATA 4 0x021b0004 0x00020024
+DATA 4 0x021b0010 0x00100A42
+DATA 4 0x021b0014 0x00000093
+DATA 4 0x021b0018 0x00001748
+DATA 4 0x021b002c 0x0f9f26d2
+DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0038 0x00190778
+DATA 4 0x021b0008 0x00000000
+DATA 4 0x021b0040 0x0000004f
+DATA 4 0x021b0000 0xc3110000
+
+DATA 4 0x021b001c 0x003f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0x82018030
+DATA 4 0x021b001c 0x04028030
+DATA 4 0x021b001c 0x02038030
+
+DATA 4 0x021b001c 0x003f8038
+DATA 4 0x021b001c 0xff0a8038
+DATA 4 0x021b001c 0x82018038
+DATA 4 0x021b001c 0x04028038
+DATA 4 0x021b001c 0x02038038
+
+DATA 4 0x021b0020 0x00001800
+DATA 4 0x021b0818 0x00000000
+DATA 4 0x021b0800 0xa1310003
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+#endif
diff --git a/board/freescale/mx6sx_19x19_arm2/plugin.S b/board/freescale/mx6sx_19x19_arm2/plugin.S
index 0a6f015..d384aeb 100644
--- a/board/freescale/mx6sx_19x19_arm2/plugin.S
+++ b/board/freescale/mx6sx_19x19_arm2/plugin.S
@@ -112,6 +112,142 @@
str r2, [r0, #0x01c]
.endm
+
+.macro imx6sx_19x19_lpddr2_arm2_ddr_setting
+ ldr r0, =IOMUXC_BASE_ADDR
+ ldr r1, =0x00080000
+ str r1, [r0, #0x618]
+ ldr r1, =0x00000000
+ str r1, [r0, #0x5fc]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x32c]
+
+ ldr r1, =0x00000030
+ str r1, [r0, #0x300]
+ str r1, [r0, #0x2fc]
+ str r1, [r0, #0x5f4]
+ str r1, [r0, #0x340]
+
+ ldr r1, =0x00000000
+ str r1, [r0, #0x320]
+ str r1, [r0, #0x310]
+ str r1, [r0, #0x314]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x614]
+
+ ldr r1, =0x00020000
+ str r1, [r0, #0x5f8]
+ ldr r1, =0x00003030
+ str r1, [r0, #0x330]
+ str r1, [r0, #0x334]
+ str r1, [r0, #0x338]
+ str r1, [r0, #0x33c]
+ ldr r1, =0x00020000
+ str r1, [r0, #0x608]
+ ldr r1, =0x00000030
+ str r1, [r0, #0x60c]
+ str r1, [r0, #0x610]
+ str r1, [r0, #0x61c]
+ str r1, [r0, #0x620]
+ str r1, [r0, #0x2ec]
+ str r1, [r0, #0x2f0]
+ str r1, [r0, #0x2f4]
+ str r1, [r0, #0x2f8]
+
+ ldr r0, =MMDC_P0_BASE_ADDR
+ ldr r2, =0x00008000
+ str r2, [r0, #0x1c]
+ ldr r2, =0x1b4700c7
+ str r2, [r0, #0x85c]
+ ldr r2, =0xa1390003
+ str r2, [r0, #0x800]
+ ldr r2, =0x00380000
+ str r2, [r0, #0x890]
+ ldr r2, =0x00000800
+ str r2, [r0, #0x8b8]
+
+ ldr r2, =0x33333333
+ str r2, [r0, #0x81c]
+ str r2, [r0, #0x820]
+ str r2, [r0, #0x824]
+ str r2, [r0, #0x828]
+
+ ldr r2, =0xf3333333
+ str r2, [r0, #0x82c]
+ str r2, [r0, #0x830]
+ str r2, [r0, #0x834]
+ str r2, [r0, #0x838]
+
+ ldr r2, =0x3e42424a
+ str r2, [r0, #0x848]
+ ldr r2, =0x38363832
+ str r2, [r0, #0x850]
+ ldr r2, =0x20000000
+ str r2, [r0, #0x83c]
+ ldr r2, =0x00000000
+ str r2, [r0, #0x840]
+ ldr r2, =0x00000800
+ str r2, [r0, #0x8b8]
+
+ ldr r2, =0x33374133
+ str r2, [r0, #0x00c]
+ ldr r2, =0x00020024
+ str r2, [r0, #0x004]
+ ldr r2, =0x00100A42
+ str r2, [r0, #0x010]
+ ldr r2, =0x00000093
+ str r2, [r0, #0x014]
+ ldr r2, =0x00001748
+ str r2, [r0, #0x018]
+ ldr r2, =0x0f9f26d2
+ str r2, [r0, #0x02c]
+ ldr r2, =0x0000020e
+ str r2, [r0, #0x030]
+ ldr r2, =0x00190778
+ str r2, [r0, #0x038]
+ ldr r2, =0x00000000
+ str r2, [r0, #0x008]
+ ldr r2, =0x0000004f
+ str r2, [r0, #0x040]
+ ldr r2, =0xc3110000
+ str r2, [r0, #0x000]
+
+ ldr r2, =0x003f8030
+ str r2, [r0, #0x01c]
+ ldr r2, =0xff0a8030
+ str r2, [r0, #0x01c]
+ ldr r2, =0x82018030
+ str r2, [r0, #0x01c]
+ ldr r2, =0x04028030
+ str r2, [r0, #0x01c]
+ ldr r2, =0x02038030
+ str r2, [r0, #0x01c]
+
+ ldr r2, =0x003f8038
+ str r2, [r0, #0x01c]
+ ldr r2, =0xff0a8038
+ str r2, [r0, #0x01c]
+ ldr r2, =0x82018038
+ str r2, [r0, #0x01c]
+ ldr r2, =0x04028038
+ str r2, [r0, #0x01c]
+ ldr r2, =0x02038038
+ str r2, [r0, #0x01c]
+
+ ldr r2, =0x00001800
+ str r2, [r0, #0x020]
+ ldr r2, =0x00000000
+ str r2, [r0, #0x818]
+ ldr r2, =0xa1310003
+ str r2, [r0, #0x800]
+ ldr r2, =0x00025576
+ str r2, [r0, #0x004]
+ ldr r2, =0x00011006
+ str r2, [r0, #0x404]
+ ldr r2, =0x00000000
+ str r2, [r0, #0x01c]
+
+.endm
.macro imx6_clock_gating
ldr r0, =CCM_BASE_ADDR
ldr r1, =0xffffffff
@@ -129,7 +265,12 @@
.endm
.macro imx6_ddr_setting
+#if defined (CONFIG_LPDDR2)
+ imx6sx_19x19_lpddr2_arm2_ddr_setting
+#else
imx6sx_19x19_ddr3_arm2_ddr_setting
+#endif
+
.endm
/* include the common plugin code here */