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author | Nitin Garg <nitin.garg@freescale.com> | 2014-05-27 10:36:06 -0500 |
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committer | Nitin Garg <nitin.garg@freescale.com> | 2014-05-27 22:15:10 -0500 |
commit | 748eac71fde78aa0c2e8cb3a3bab94bd994c06f5 (patch) | |
tree | 3ccd5be6ad3a4b21018a00fee6426b8612e6d83a /board/freescale/mx6sabresd | |
parent | 441fd86d055c57b79257943449a8101b83e98c61 (diff) | |
download | u-boot-imx-748eac71fde78aa0c2e8cb3a3bab94bd994c06f5.zip u-boot-imx-748eac71fde78aa0c2e8cb3a3bab94bd994c06f5.tar.gz u-boot-imx-748eac71fde78aa0c2e8cb3a3bab94bd994c06f5.tar.bz2 |
ENGR00315499-5: Support i.MX6 1.2GHz via LDO bypass
Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz,
enable LDO bypass and setup PMIC voltages. LDO bypass is dependent
on the flatten device tree file.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Diffstat (limited to 'board/freescale/mx6sabresd')
-rw-r--r-- | board/freescale/mx6sabresd/mx6sabresd.c | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index d7d932e..722981e 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -24,6 +24,10 @@ #include <ipu_pixfmt.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> +#ifdef CONFIG_SYS_I2C_MXC +#include <i2c.h> +#include <asm/imx-common/mxc_i2c.h> +#endif DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ @@ -156,6 +160,68 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned char value; + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + /* increase VDDARM to 1.425V */ + if (i2c_read(0x8, 0x20, 1, &value, 1)) { + printf("Read SW1AB error!\n"); + return; + } + value &= ~0x3f; + value |= 0x2d; + if (i2c_write(0x8, 0x20, 1, &value, 1)) { + printf("Set SW1AB error!\n"); + return; + } + /* increase VDDSOC to 1.425V */ + if (i2c_read(0x8, 0x2e, 1, &value, 1)) { + printf("Read SW1C error!\n"); + return; + } + value &= ~0x3f; + value |= 0x2d; + if (i2c_write(0x8, 0x2e, 1, &value, 1)) { + printf("Set SW1C error!\n"); + return; + } + } + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + /* decrease VDDARM to 1.175V */ + if (i2c_read(0x8, 0x20, 1, &value, 1)) { + printf("Read SW1AB error!\n"); + return; + } + value &= ~0x3f; + value |= 0x23; + if (i2c_write(0x8, 0x20, 1, &value, 1)) { + printf("Set SW1AB error!\n"); + return; + } + /* increase VDDSOC to 1.175V */ + if (i2c_read(0x8, 0x2e, 1, &value, 1)) { + printf("Read SW1C error!\n"); + return; + } + value &= ~0x3f; + value |= 0x23; + if (i2c_write(0x8, 0x2e, 1, &value, 1)) { + printf("Set SW1C error!\n"); + return; + } + + set_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[3] = { {USDHC2_BASE_ADDR}, @@ -516,3 +582,4 @@ int checkboard(void) puts("Board: MX6-SabreSD\n"); return 0; } + |