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| author | Peng Fan <peng.fan@nxp.com> | 2016-02-25 16:52:49 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 14:04:40 +0800 |
| commit | f541f0078dfaa73f212acded213bf66b5ed79087 (patch) | |
| tree | 04f93c52ce22afab8deb8028f0457f868d0722d4 /board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg | |
| parent | 4798ccf62379676c744a58d109eee39efd9d3d62 (diff) | |
| download | u-boot-imx-f541f0078dfaa73f212acded213bf66b5ed79087.zip u-boot-imx-f541f0078dfaa73f212acded213bf66b5ed79087.tar.gz u-boot-imx-f541f0078dfaa73f212acded213bf66b5ed79087.tar.bz2 | |
MLK-12436-9: mx6sabresd: update ddr script
Align ddr script with imx_v2016.03 latest ddr script.
mx6qp.cfg is 1.13 version
http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4
http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1
arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI
arik_r2_sdb_ddr3_528_1.13.inc is for sabresd
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 39c2989e6ba0de6b35b2d93acd9d67f889ab4b39)
Diffstat (limited to 'board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg')
| -rw-r--r-- | board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg new file mode 100644 index 0000000..b792225 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Jason Liu <r64343@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4, 0x020e0774, 0x000C0000 +DATA 4, 0x020e0754, 0x00000000 +DATA 4, 0x020e04ac, 0x00000030 +DATA 4, 0x020e04b0, 0x00000030 +DATA 4, 0x020e0464, 0x00000030 +DATA 4, 0x020e0490, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e0494, 0x00000030 +DATA 4, 0x020e04a0, 0x00000000 +DATA 4, 0x020e04b4, 0x00000030 +DATA 4, 0x020e04b8, 0x00000030 +DATA 4, 0x020e076c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e04bc, 0x00000030 +DATA 4, 0x020e04c0, 0x00000030 +DATA 4, 0x020e04c4, 0x00000030 +DATA 4, 0x020e04c8, 0x00000030 +DATA 4, 0x020e0760, 0x00020000 +DATA 4, 0x020e0764, 0x00000030 +DATA 4, 0x020e0770, 0x00000030 +DATA 4, 0x020e0778, 0x00000030 +DATA 4, 0x020e077c, 0x00000030 +DATA 4, 0x020e0470, 0x00000030 +DATA 4, 0x020e0474, 0x00000030 +DATA 4, 0x020e0478, 0x00000030 +DATA 4, 0x020e047c, 0x00000030 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001F001F +DATA 4, 0x021b0810, 0x001F001F +DATA 4, 0x021b083c, 0x42190219 +DATA 4, 0x021b0840, 0x017B0177 +DATA 4, 0x021b0848, 0x4B4D4E4D +DATA 4, 0x021b0850, 0x3F3E2D36 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b0004, 0x0002002D +DATA 4, 0x021b0008, 0x00333030 +DATA 4, 0x021b000c, 0x3F435313 +DATA 4, 0x021b0010, 0xB66E8B63 +DATA 4, 0x021b0014, 0x01FF00DB +DATA 4, 0x021b0018, 0x00001740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x00431023 +DATA 4, 0x021b0040, 0x00000017 +DATA 4, 0x021b0000, 0x83190000 +DATA 4, 0x021b001c, 0x04008032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x05208030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b0004, 0x0002556D +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFC000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F +#endif |