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| author | Eric Nelson <eric.nelson@boundarydevices.com> | 2012-01-31 07:52:05 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-02-27 21:19:23 +0100 |
| commit | 373a1d8c0ee150bb3680722c5b888662e0e08291 (patch) | |
| tree | d7bbea52a4d39c687311570b0e546b54af9cc655 /board/freescale/mx6qsabrelite | |
| parent | d5c37c9cc45ee400e0f53ba0e11edc88d6bd630b (diff) | |
| download | u-boot-imx-373a1d8c0ee150bb3680722c5b888662e0e08291.zip u-boot-imx-373a1d8c0ee150bb3680722c5b888662e0e08291.tar.gz u-boot-imx-373a1d8c0ee150bb3680722c5b888662e0e08291.tar.bz2 | |
mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Jason Liu <jason.hui@linaro.org>
Diffstat (limited to 'board/freescale/mx6qsabrelite')
| -rw-r--r-- | board/freescale/mx6qsabrelite/imximage.cfg | 2 | ||||
| -rw-r--r-- | board/freescale/mx6qsabrelite/mx6qsabrelite.c | 25 |
2 files changed, 26 insertions, 1 deletions
diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg index 83dee6f..c389427 100644 --- a/board/freescale/mx6qsabrelite/imximage.cfg +++ b/board/freescale/mx6qsabrelite/imximage.cfg @@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006 # set the default clock gate to save power DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC00 +DATA 4 0x020c406c 0x0030FC03 DATA 4 0x020c4070 0x0FFFC000 DATA 4 0x020c4074 0x3FF00000 DATA 4 0x020c4078 0x00FFF300 diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index a53b01f..97a77e8 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -193,6 +197,23 @@ int board_mmc_init(bd_t *bis) } #endif +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t ecspi1_pads[] = { + /* SS1 */ + MX6Q_PAD_EIM_D19__GPIO_3_19 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +void setup_spi(void) +{ + gpio_direction_output(GPIO_NUMBER(3, 19), 1); + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); +} +#endif + #define MII_1000BASET_CTRL 0x9 #define MII_EXTENDED_CTRL 0xb #define MII_EXTENDED_DATAW 0xc @@ -239,6 +260,10 @@ int board_eth_init(bd_t *bis) return ret; } +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + return 0; } |