diff options
| author | Bai Ping <b51503@freescale.com> | 2015-10-30 00:15:20 +0800 |
|---|---|---|
| committer | Bai Ping <b51503@freescale.com> | 2015-10-30 22:28:39 +0800 |
| commit | 55a80625e81ea9ff5a5286f1d2183a2f0900f5c3 (patch) | |
| tree | bfef454b709462b8ecb15ee1c2828c8c6e7bff7c /board/freescale/mx6qsabreauto | |
| parent | 603b89c8990868c51b1546db4877d198358485ff (diff) | |
| download | u-boot-imx-55a80625e81ea9ff5a5286f1d2183a2f0900f5c3.zip u-boot-imx-55a80625e81ea9ff5a5286f1d2183a2f0900f5c3.tar.gz u-boot-imx-55a80625e81ea9ff5a5286f1d2183a2f0900f5c3.tar.bz2 | |
MLK-11795-01 imx: correct the vdd_arm regulator setting on imx6qp
on i.MX6QP SDB board, the SW1A/B/C regulator is used by
VDD_SOC_IN, the regulator of VDD_ARM_IN is SW2, the voltage
setting for VDD_ARM_IN should be corresponding to SW2. So fix
the regulator mismatch issue on i.MX6QP SDB board.
Signed-off-by: Bai Ping <b51503@freescale.com>
Diffstat (limited to 'board/freescale/mx6qsabreauto')
| -rw-r--r-- | board/freescale/mx6qsabreauto/mx6qsabreauto.c | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index e701828..6dcc2dc 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -812,6 +812,13 @@ int power_init_board(void) value &= ~0x3f; value |= 0x17; pmic_reg_write(pfuze, PFUZE100_SW2STBY, value); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW2CONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW2CONF, value); + } return 0; @@ -832,12 +839,20 @@ void ldo_mode_set(int ldo_bypass) if (check_1_2G()) { ldo_bypass = 0; /* ldo_enable on 1.2G chip */ printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); - /* increase VDDARM to 1.425V */ - pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); - value &= ~0x3f; - value |= 0x2d; - pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + if (is_mx6dqp()) { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW2VOL, &value); + value &= ~0x3f; + value |= 0x29; + pmic_reg_write(p, PFUZE100_SW2VOL, value); + } else { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + } /* increase VDDSOC to 1.425V */ pmic_reg_read(p, PFUZE100_SW1CVOL, &value); value &= ~0x3f; |