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| author | Ye.Li <B37916@freescale.com> | 2015-03-23 17:33:43 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-04-29 15:03:07 +0800 |
| commit | 76885e14fa8aa562fd2f02c53f1b5a5784678e51 (patch) | |
| tree | 8d274945fe057b9c17cb12095b59b04bc0cecbc0 /board/freescale/mx6qsabreauto/mx6qsabreauto.c | |
| parent | 0d631cb912e3c75b8c140cc483c40c3c5984d2d6 (diff) | |
| download | u-boot-imx-76885e14fa8aa562fd2f02c53f1b5a5784678e51.zip u-boot-imx-76885e14fa8aa562fd2f02c53f1b5a5784678e51.tar.gz u-boot-imx-76885e14fa8aa562fd2f02c53f1b5a5784678e51.tar.bz2 | |
MLK-10448-6 imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board support
1. Add DDR script v1.04 for i.MX6DQP SABREAUTO board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit e0b316f071aa17c8e41a50f395346ab9f012e665)
Conflicts:
board/freescale/mx6qsabreauto/mx6qsabreauto.c
boards.cfg
Diffstat (limited to 'board/freescale/mx6qsabreauto/mx6qsabreauto.c')
| -rw-r--r-- | board/freescale/mx6qsabreauto/mx6qsabreauto.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index e9b4fe0..7989669 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -452,7 +452,12 @@ static int setup_fec(void) { int ret; +#ifdef CONFIG_MX6QP + imx_iomux_set_gpr_register(5, 9, 1, 1); +#else imx_iomux_set_gpr_register(1, 21, 1, 1); +#endif + ret = enable_fec_anatop_clock(0, ENET_125MHZ); if (ret) return ret; @@ -679,10 +684,20 @@ int board_init(void) static struct pmic *pfuze; int power_init_board(void) { + unsigned int value; + pfuze = pfuze_common_init(I2C_PMIC); if (!pfuze) return -ENODEV; + if (is_mx6dqp()) { + /* set SW2 staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW2STBY, &value); + value &= ~0x3f; + value |= 0x17; + pmic_reg_write(pfuze, PFUZE100_SW2STBY, value); + } + return pfuze_mode_init(pfuze, APS_PFM); } |