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authorAdrian Alonso <adrian.alonso@nxp.com>2016-01-20 15:16:08 -0600
committerguoyin.chen <guoyin.chen@freescale.com>2016-03-04 15:35:57 +0800
commit21c6f85d0023a5c7edf17b31d4334beb966d8059 (patch)
treec7eb9ec8e611096b688bfaf721079394995764ad /board/freescale/mx6qarm2/mx6qarm2.c
parent742ab69302700dc9137329b4773de1aa0f5df89f (diff)
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MLK-12442: imx: mx6qarm2: lpddr2 set dram 2 channel fixed mode
Setup MMDC in two channel fixed mode Initialize dram banks for two channel fixed mode DRAM bank = 0x00000000 -> start = 0x10000000 -> size = 0x20000000 DRAM bank = 0x00000001 -> start = 0x80000000 -> size = 0x20000000 Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Diffstat (limited to 'board/freescale/mx6qarm2/mx6qarm2.c')
-rw-r--r--board/freescale/mx6qarm2/mx6qarm2.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
index 188096b..72f59ef 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -47,6 +47,15 @@ int dram_init(void)
return 0;
}
+#if defined(CONFIG_MX6DQ_POP_LPDDR2)
+void dram_init_banksize(void) {
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+ gd->bd->bi_dram[0].size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[1].size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
+}
+#endif
+
iomux_v3_cfg_t const uart4_pads[] = {
MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),