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authorFugang Duan <B38611@freescale.com>2012-12-26 13:20:11 +0800
committerFugang Duan <B38611@freescale.com>2013-01-08 17:32:08 +0800
commit7e5dab8c5310f82637773255d475a9967e38284b (patch)
tree10306e518300da944fb85fad27b4be60bc3589ec /board/freescale/mx6q_sabresd
parentd0e1fff03a24d2dbbc6bc61a65bdd37f6c241b82 (diff)
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ENGR00230437: mx6: epdc: EPDC I/O setup after V3p3 is enable
EPDC will be used when splash screen is shown, EPDC io setup is done before 3V3 digitial power, which cause critical chip burn-out for all platforms. To follow the E-Ink specification, setup EPDC I/O after V3p3 is enable. Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'board/freescale/mx6q_sabresd')
-rw-r--r--board/freescale/mx6q_sabresd/mx6q_sabresd.c153
1 files changed, 94 insertions, 59 deletions
diff --git a/board/freescale/mx6q_sabresd/mx6q_sabresd.c b/board/freescale/mx6q_sabresd/mx6q_sabresd.c
index 7be4d26..1b898da 100644
--- a/board/freescale/mx6q_sabresd/mx6q_sabresd.c
+++ b/board/freescale/mx6q_sabresd/mx6q_sabresd.c
@@ -1108,7 +1108,7 @@ int board_mmc_init(bd_t *bis)
#ifdef CONFIG_MXC_EPDC
#ifdef CONFIG_SPLASH_SCREEN
-int setup_splash_img()
+int setup_splash_img(void)
{
#ifdef CONFIG_SPLASH_IS_IN_MMC
int mmc_dev = get_mmc_env_devno();
@@ -1146,6 +1146,8 @@ int setup_splash_img()
return (n == blk_cnt) ? 0 : -1;
#endif
+
+ return 0;
}
#endif
@@ -1180,7 +1182,7 @@ struct epdc_timing_params panel_timings = {
.num_ce = 1,
};
-static void setup_epdc_power()
+static void setup_epdc_power(void)
{
unsigned int reg;
@@ -1212,66 +1214,13 @@ static void setup_epdc_power()
writel(reg, GPIO2_BASE_ADDR + GPIO_GDIR);
}
-void epdc_power_on()
-{
- unsigned int reg;
-
- /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
- reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
- reg |= (1 << 20);
- writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-
- /* Set PMIC Wakeup to high - enable Display power */
- reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
- reg |= (1 << 20);
- writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-
- /* Wait for PWRGOOD == 1 */
- while (1) {
- reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
- if (!(reg & (1 << 21)))
- break;
-
- udelay(100);
- }
-
- /* Enable VCOM */
- reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
- reg |= (1 << 17);
- writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-
- reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
-
- udelay(500);
-}
-
-void epdc_power_off()
-{
- unsigned int reg;
- /* Set PMIC Wakeup to low - disable Display power */
- reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
- reg &= ~(1 << 20);
- writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-
- /* Disable VCOM */
- reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
- reg &= ~(1 << 17);
- writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
-
- /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
- reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
- reg &= ~(1 << 20);
- writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
-}
-
-int setup_waveform_file()
+int setup_waveform_file(void)
{
#ifdef CONFIG_WAVEFORM_FILE_IN_MMC
int mmc_dev = get_mmc_env_devno();
ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
ulong size = CONFIG_WAVEFORM_FILE_SIZE;
ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
- char *s = NULL;
struct mmc *mmc = find_mmc_device(mmc_dev);
uint blk_start, blk_cnt, n;
@@ -1298,10 +1247,8 @@ int setup_waveform_file()
#endif
}
-static void setup_epdc()
+static void epdc_enable_pins(void)
{
- unsigned int reg;
-
/* epdc iomux settings */
mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A16__EPDC_SDDO_0);
mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA10__EPDC_SDDO_1);
@@ -1323,6 +1270,36 @@ static void setup_epdc()
mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA4__EPDC_SDCE_0);
mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA5__EPDC_SDCE_1);
mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA6__EPDC_SDCE_2);
+}
+
+static void epdc_disable_pins(void)
+{
+ /* Configure MUX settings for EPDC pins to GPIO */
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A16__GPIO_2_22);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA10__GPIO_3_10);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA12__GPIO_3_12);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA11__GPIO_3_11);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_LBA__GPIO_2_27);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_EB2__GPIO_2_30);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_CS0__GPIO_2_23);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_RW__GPIO_2_26);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A21__GPIO_2_17);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A22__GPIO_2_16);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A23__GPIO_6_6);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_A24__GPIO_5_4);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D31__GPIO_3_31);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D27__GPIO_3_27);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA1__GPIO_3_1);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_EB1__GPIO_2_29);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA2__GPIO_3_2);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA4__GPIO_3_4);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA5__GPIO_3_5);
+ mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_DA6__GPIO_3_6);
+}
+
+static void setup_epdc(void)
+{
+ unsigned int reg;
/*** epdc Maxim PMIC settings ***/
@@ -1385,6 +1362,64 @@ static void setup_epdc()
/* Assign fb_base */
gd->fb_base = CONFIG_FB_BASE;
}
+
+void epdc_power_on()
+{
+ unsigned int reg;
+
+ /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+ reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+ reg |= (1 << 20);
+ writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+ udelay(1000);
+
+ /* Enable epdc signal pin */
+ epdc_enable_pins();
+
+ /* Set PMIC Wakeup to high - enable Display power */
+ reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+ reg |= (1 << 20);
+ writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+
+ /* Wait for PWRGOOD == 1 */
+ while (1) {
+ reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+ if (!(reg & (1 << 21)))
+ break;
+
+ udelay(100);
+ }
+
+ /* Enable VCOM */
+ reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+ reg |= (1 << 17);
+ writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+
+ reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+
+ udelay(500);
+}
+
+void epdc_power_off()
+{
+ unsigned int reg;
+ /* Set PMIC Wakeup to low - disable Display power */
+ reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+ reg &= ~(1 << 20);
+ writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+
+ /* Disable VCOM */
+ reg = readl(GPIO3_BASE_ADDR + GPIO_DR);
+ reg &= ~(1 << 17);
+ writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
+
+ epdc_disable_pins();
+
+ /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+ reg = readl(GPIO2_BASE_ADDR + GPIO_DR);
+ reg &= ~(1 << 20);
+ writel(reg, GPIO2_BASE_ADDR + GPIO_DR);
+}
#endif
/* For DDR mode operation, provide target delay parameter for each SD port.