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authorLiu Ying <Ying.Liu@freescale.com>2012-07-27 12:49:51 +0800
committerLiu Ying <Ying.Liu@freescale.com>2012-07-31 10:11:23 +0800
commit1304702c69a3d7bfdaa407c74d498bf8b6431eb2 (patch)
tree7dcfb9dc675a0ffaa5339bf44abeffd1a216574a /board/freescale/mx6q_sabresd
parent1c325b0236df114e2e74de0cd02521c2398e15dc (diff)
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ENGR00218583-1 MX6Q/DL SabreSD:Support LVDS1 splashimage
This patch configures iomux gpr3 register to enable LVDS1 via IPU1 DI1 if user chooses to use it. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Diffstat (limited to 'board/freescale/mx6q_sabresd')
-rw-r--r--board/freescale/mx6q_sabresd/mx6q_sabresd.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/board/freescale/mx6q_sabresd/mx6q_sabresd.c b/board/freescale/mx6q_sabresd/mx6q_sabresd.c
index 0bfd700..09b8f1d 100644
--- a/board/freescale/mx6q_sabresd/mx6q_sabresd.c
+++ b/board/freescale/mx6q_sabresd/mx6q_sabresd.c
@@ -1393,6 +1393,15 @@ void lcd_enable(void)
reg = 0x0002A953;
writel(reg, CCM_BASE_ADDR + CLKCTL_CHSCCDR);
+ /*
+ * LVDS0 mux to IPU1 DI0.
+ * LVDS1 mux to IPU1 DI1.
+ */
+ reg = readl(IOMUXC_BASE_ADDR + 0xC);
+ reg &= ~(0x000003C0);
+ reg |= 0x00000100;
+ writel(reg, IOMUXC_BASE_ADDR + 0xC);
+
if (di == 1)
writel(0x40C, IOMUXC_BASE_ADDR + 0x8);
else