ENGR00161004 MX6Q Uboot Rename sabreauto to arm2 board

Sabreauto is an inaccurate name for the Armadillo2 board that
this code is actually meant for. So, replaced "sabreauto" in folder names,
file names, configs, and code with "arm2". Created a new machine id for
ARM2 board.

Signed-off-by: Anish Trivedi <anish@freescale.com>

6 files changed, 0 insertions, 1438 deletions

diff --git a/board/freescale/mx6q_sabreauto/Makefile b/board/freescale/mx6q_sabreauto/Makefile
deleted file mode 100644
index 60e5fc4..0000000
--- a/board/freescale/mx6q_sabreauto/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-#
-# (C) Copyright 2010-2011 Freescale Semiconductor, Inc.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS	:= mx6q_sabreauto.o
-SOBJS	:= lowlevel_init.o flash_header.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/freescale/mx6q_sabreauto/config.mk b/board/freescale/mx6q_sabreauto/config.mk
deleted file mode 100644
index a0ce2a1..0000000
--- a/board/freescale/mx6q_sabreauto/config.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
-
-sinclude $(OBJTREE)/board/$(VENDOR)/$(BOARD)/config.tmp
-
-ifndef TEXT_BASE
-	TEXT_BASE = 0x27800000
-endif
diff --git a/board/freescale/mx6q_sabreauto/flash_header.S b/board/freescale/mx6q_sabreauto/flash_header.S
deleted file mode 100644
index 441694e..0000000
--- a/board/freescale/mx6q_sabreauto/flash_header.S
+++ /dev/null
@@ -1,356 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx6.h>
-
-#ifdef	CONFIG_FLASH_HEADER
-#ifndef CONFIG_FLASH_HEADER_OFFSET
-# error "Must define the offset of flash header"
-#endif
-
-#define CPU_2_BE_32(l) \
-       ((((l) & 0x000000FF) << 24) | \
-	(((l) & 0x0000FF00) << 8)  | \
-	(((l) & 0x00FF0000) >> 8)  | \
-	(((l) & 0xFF000000) >> 24))
-
-#define MXC_DCD_ITEM(i, addr, val)   \
-dcd_node_##i:                        \
-        .word CPU_2_BE_32(addr) ;     \
-        .word CPU_2_BE_32(val)  ;     \
-
-.section ".text.flasheader", "x"
-	b	_start
-	.org	CONFIG_FLASH_HEADER_OFFSET
-
-ivt_header:       .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
-app_code_jump_v:  .word _start
-reserv1:          .word 0x0
-dcd_ptr:          .word dcd_hdr
-boot_data_ptr:	  .word boot_data
-self_ptr:         .word ivt_header
-app_code_csf:     .word 0x0
-reserv2:          .word 0x0
-
-boot_data:        .word TEXT_BASE
-image_len:        .word _end_of_copy  - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
-plugin:           .word 0x0
-
-#ifdef CONFIG_LPDDR2
-
-dcd_hdr:          .word 0x400804D2 /* Tag=0xD2, Len=128*8 + 4 + 4, Ver=0x40 */
-write_dcd_cmd:    .word 0x040404CC /* Tag=0xCC, Len=128*8 + 4, Param=0x04 */
-
-/* DCD */
-MXC_DCD_ITEM(1, CCM_BASE_ADDR + 0x18, 0x60324)
-
-MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5a8, 0x00003038)
-MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x5b0, 0x00003038)
-MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x524, 0x00003038)
-MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x51c, 0x00003038)
-
-MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x518, 0x00003038)
-MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x50c, 0x00003038)
-MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5b8, 0x00003038)
-MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5c0, 0x00003038)
-
-MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5ac, 0x00000038)
-MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x5b4, 0x00000038)
-MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x528, 0x00000038)
-MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x520, 0x00000038)
-
-MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x514, 0x00000038)
-MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x510, 0x00000038)
-MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5bc, 0x00000038)
-MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5c4, 0x00000038)
-
-MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x56c, 0x00000038)
-MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x578, 0x00000038)
-MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x588, 0x00000038)
-MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x594, 0x00000038)
-
-MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x57c, 0x00000038)
-MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x590, 0x00000038)
-MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x598, 0x00000038)
-MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
-
-MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x59c, 0x00000038)
-MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x5a0, 0x00000038)
-MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x784, 0x00000038)
-MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x788, 0x00000038)
-
-MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x794, 0x00000038)
-MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x79c, 0x00000038)
-MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a0, 0x00000038)
-MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a4, 0x00000038)
-
-MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x7a8, 0x00000038)
-MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x748, 0x00000038)
-MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x74c, 0x00000038)
-MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
-
-MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
-MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
-MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x78c, 0x00000038)
-MXC_DCD_ITEM(41, IOMUXC_BASE_ADDR + 0x798, 0x00080000)
-
-MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
-MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x01c, 0x00008000)
-
-MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x85c, 0x1b5f01ff)
-MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x85c, 0x1b5f01ff)
-
-MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x800, 0xa1390000)
-MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x800, 0xa1390000)
-
-MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x890, 0x00400000)
-MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x890, 0x00400000)
-
-MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x8bc, 0x00055555)
-
-MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
-MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
-
-MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
-MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
-MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
-MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
-MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
-MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
-MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
-MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
-
-MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x82c, 0xf3333333)
-MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x830, 0xf3333333)
-MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x834, 0xf3333333)
-MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x838, 0xf3333333)
-MXC_DCD_ITEM(65, MMDC_P1_BASE_ADDR + 0x82c, 0xf3333333)
-MXC_DCD_ITEM(66, MMDC_P1_BASE_ADDR + 0x830, 0xf3333333)
-MXC_DCD_ITEM(67, MMDC_P1_BASE_ADDR + 0x834, 0xf3333333)
-MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x838, 0xf3333333)
-
-MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x848, 0x49383b39)
-MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x850, 0x30364738)
-MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x848, 0x3e3c3846)
-MXC_DCD_ITEM(72, MMDC_P1_BASE_ADDR + 0x850, 0x4c294b35)
-
-MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000)
-MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x840, 0x0)
-MXC_DCD_ITEM(75, MMDC_P1_BASE_ADDR + 0x83c, 0x20000000)
-MXC_DCD_ITEM(76, MMDC_P1_BASE_ADDR + 0x840, 0x0)
-
-MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x858, 0xf00)
-MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x858, 0xf00)
-
-MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
-MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
-
-MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0xc, 0x555a61a5)
-MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x4, 0x20036)
-MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x10, 0x160e83)
-MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x14, 0xdd)
-MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x18, 0x8174c)
-MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x2c, 0xf9f26d2)
-MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x30, 0x20e)
-MXC_DCD_ITEM(88, MMDC_P0_BASE_ADDR + 0x38, 0x200aac)
-MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x8, 0x0)
-
-MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x40, 0x5f)
-
-MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x0, 0xc3010000)
-
-MXC_DCD_ITEM(92, MMDC_P1_BASE_ADDR + 0xc, 0x555a61a5)
-MXC_DCD_ITEM(93, MMDC_P1_BASE_ADDR + 0x4, 0x20036)
-MXC_DCD_ITEM(94, MMDC_P1_BASE_ADDR + 0x10, 0x160e83)
-MXC_DCD_ITEM(95, MMDC_P1_BASE_ADDR + 0x14, 0xdd)
-MXC_DCD_ITEM(96, MMDC_P1_BASE_ADDR + 0x18, 0x8174c)
-MXC_DCD_ITEM(97, MMDC_P1_BASE_ADDR + 0x2c, 0xf9f26d2)
-MXC_DCD_ITEM(98, MMDC_P1_BASE_ADDR + 0x30, 0x20e)
-MXC_DCD_ITEM(99, MMDC_P1_BASE_ADDR + 0x38, 0x200aac)
-MXC_DCD_ITEM(100, MMDC_P1_BASE_ADDR + 0x8, 0x0)
-
-MXC_DCD_ITEM(101, MMDC_P1_BASE_ADDR + 0x40, 0x3f)
-MXC_DCD_ITEM(102, MMDC_P1_BASE_ADDR + 0x0, 0xc3010000)
-
-MXC_DCD_ITEM(103, MMDC_P0_BASE_ADDR + 0x1c, 0x3f8030)
-MXC_DCD_ITEM(104, MMDC_P0_BASE_ADDR + 0x1c, 0xff0a8030)
-MXC_DCD_ITEM(105, MMDC_P0_BASE_ADDR + 0x1c, 0xc2018030)
-MXC_DCD_ITEM(106, MMDC_P0_BASE_ADDR + 0x1c, 0x6028030)
-MXC_DCD_ITEM(107, MMDC_P0_BASE_ADDR + 0x1c, 0x2038030)
-
-MXC_DCD_ITEM(108, MMDC_P1_BASE_ADDR + 0x1c, 0x3f8030)
-MXC_DCD_ITEM(109, MMDC_P1_BASE_ADDR + 0x1c, 0xff0a8030)
-MXC_DCD_ITEM(110, MMDC_P1_BASE_ADDR + 0x1c, 0xc2018030)
-MXC_DCD_ITEM(111, MMDC_P1_BASE_ADDR + 0x1c, 0x6028030)
-MXC_DCD_ITEM(112, MMDC_P1_BASE_ADDR + 0x1c, 0x2038030)
-
-MXC_DCD_ITEM(113, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
-MXC_DCD_ITEM(114, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
-
-MXC_DCD_ITEM(115, MMDC_P0_BASE_ADDR + 0x20, 0x7800)
-MXC_DCD_ITEM(116, MMDC_P1_BASE_ADDR + 0x20, 0x7800)
-
-MXC_DCD_ITEM(117, MMDC_P0_BASE_ADDR + 0x818, 0x0)
-MXC_DCD_ITEM(118, MMDC_P1_BASE_ADDR + 0x818, 0x0)
-
-MXC_DCD_ITEM(119, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
-MXC_DCD_ITEM(120, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
-
-MXC_DCD_ITEM(121, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
-MXC_DCD_ITEM(122, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
-
-MXC_DCD_ITEM(123, MMDC_P0_BASE_ADDR + 0x1c, 0x0)
-MXC_DCD_ITEM(124, MMDC_P1_BASE_ADDR + 0x1c, 0x0)
-
-MXC_DCD_ITEM(125, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
-
-/* enable AXI cache for VDOA/VPU/IPU */
-MXC_DCD_ITEM(126, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
-/* set IPU Qos=0x7 */
-MXC_DCD_ITEM(127, IOMUXC_BASE_ADDR + 0x018, 0x00070007)
-MXC_DCD_ITEM(128, IOMUXC_BASE_ADDR + 0x01c, 0x00070007)
-
-#else
-
-dcd_hdr:          .word 0x40F002D2 /* Tag=0xD2, Len=93*8 + 4 + 4, Ver=0x40 */
-write_dcd_cmd:    .word 0x04EC02CC /* Tag=0xCC, Len=93*8 + 4, Param=0x04 */
-
-/* DCD */
-
-MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030)
-MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030)
-MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x524, 0x00000030)
-MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x51c, 0x00000030)
-
-MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x518, 0x00000030)
-MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x50c, 0x00000030)
-MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030)
-MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030)
-
-MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5ac, 0x00020030)
-MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5b4, 0x00020030)
-MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x528, 0x00020030)
-MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x520, 0x00020030)
-
-MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x514, 0x00020030)
-MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x510, 0x00020030)
-MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5bc, 0x00020030)
-MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5c4, 0x00020030)
-
-MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x56c, 0x00020030)
-MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x578, 0x00020030)
-MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x588, 0x00020030)
-MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x594, 0x00020030)
-
-MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x57c, 0x00020030)
-MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x590, 0x00003000)
-MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x598, 0x00003000)
-MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
-
-MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x59c, 0x00003030)
-MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030)
-MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x784, 0x00000030)
-MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x788, 0x00000030)
-
-MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x794, 0x00000030)
-MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x79c, 0x00000030)
-MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030)
-MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030)
-
-MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030)
-MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x748, 0x00000030)
-MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
-MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
-
-MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
-MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
-MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
-MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
-
-MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
-MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
-MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
-MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
-
-MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
-MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
-MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
-MXC_DCD_ITEM(48, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
-
-MXC_DCD_ITEM(49, MMDC_P0_BASE_ADDR + 0x018, 0x00081740)
-
-MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
-MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x00c, 0x555A7975)
-MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x010, 0xFF538E64)
-MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
-MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
-
-MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x030, 0x005B0E21)
-MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
-MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
-MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x040, 0x00000027)
-MXC_DCD_ITEM(59, MMDC_P0_BASE_ADDR + 0x000, 0xC31A0000)
-
-MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
-MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x01c, 0x0408803A)
-MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
-MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803B)
-MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031)
-MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039)
-MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
-MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x01c, 0x09408038)
-
-MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
-MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048)
-MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x800, 0xA1380003)
-MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x800, 0xA1380003)
-MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
-MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x818, 0x00022227)
-MXC_DCD_ITEM(74, MMDC_P1_BASE_ADDR + 0x818, 0x00022227)
-
-MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x83c, 0x434B0350)
-MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x840, 0x034C0359)
-MXC_DCD_ITEM(77, MMDC_P1_BASE_ADDR + 0x83c, 0x434B0350)
-MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x840, 0x03650348)
-MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x848, 0x4436383B)
-MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x848, 0x39393341)
-MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x850, 0x35373933)
-MXC_DCD_ITEM(82, MMDC_P1_BASE_ADDR + 0x850, 0x48254A36)
-
-MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F)
-MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F)
-
-MXC_DCD_ITEM(85, MMDC_P1_BASE_ADDR + 0x80c, 0x00440044)
-MXC_DCD_ITEM(86, MMDC_P1_BASE_ADDR + 0x810, 0x00440044)
-
-MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
-MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
-
-MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
-MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
-
-/* enable AXI cache for VDOA/VPU/IPU */
-MXC_DCD_ITEM(91, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
-/* set IPU Qos=0x7 */
-MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x018, 0x00070007)
-MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x01c, 0x00070007)
-#endif
-
-#endif
diff --git a/board/freescale/mx6q_sabreauto/lowlevel_init.S b/board/freescale/mx6q_sabreauto/lowlevel_init.S
deleted file mode 100644
index 2ac77b9..0000000
--- a/board/freescale/mx6q_sabreauto/lowlevel_init.S
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/mx6.h>
-
-/*
- Disable L2Cache because ROM turn it on when uboot use plug-in.
- If L2Cache is on default, there are cache coherence problem if kernel have
- not config L2Cache.
-*/
-.macro init_l2cc
-    ldr     r1, =0xa02000
-    ldr     r0, =0x0
-    str     r0, [r1, #0x100]
-.endm /* init_l2cc */
-
-/* invalidate the D-CACHE */
-.macro inv_dcache
-    mov     r0,#0
-    mcr     p15,2,r0,c0,c0,0  /* cache size selection register, select dcache */
-    mrc     p15,1,r0,c0,c0,0  /* cache size ID register */
-    mov     r0,r0,ASR #13
-    ldr     r3,=0xfff
-    and     r0,r0,r3
-    cmp     r0,#0x7f
-    moveq   r6,#0x1000
-    beq     size_done
-    cmp     r0,#0xff
-    moveq   r6,#0x2000
-    movne   r6,#0x4000
-
-size_done:
-    mov     r2,#0
-    mov     r3,#0x40000000
-    mov     r4,#0x80000000
-    mov     r5,#0xc0000000
-
-d_inv_loop:
-    mcr     p15,0,r2,c7,c6,2  /* invalidate dcache by set / way */
-    mcr     p15,0,r3,c7,c6,2  /* invalidate dcache by set / way */
-    mcr     p15,0,r4,c7,c6,2  /* invalidate dcache by set / way */
-    mcr     p15,0,r5,c7,c6,2  /* invalidate dcache by set / way */
-    add     r2,r2,#0x20
-    add     r3,r3,#0x20
-    add     r4,r4,#0x20
-    add     r5,r5,#0x20
-
-    cmp     r2,r6
-    bne     d_inv_loop
-.endm
-
-/* AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
-	/*
-	 * Set all MPROTx to be non-bufferable, trusted for R/W,
-	 * not forced to user-mode.
-	 */
-	ldr r0, =AIPS1_ON_BASE_ADDR
-	ldr r1, =0x77777777
-	str r1, [r0, #0x0]
-	str r1, [r0, #0x4]
-	ldr r1, =0x0
-	str r1, [r0, #0x40]
-	str r1, [r0, #0x44]
-	str r1, [r0, #0x48]
-	str r1, [r0, #0x4C]
-	str r1, [r0, #0x50]
-
-	ldr r0, =AIPS2_ON_BASE_ADDR
-	ldr r1, =0x77777777
-	str r1, [r0, #0x0]
-	str r1, [r0, #0x4]
-	ldr r1, =0x0
-	str r1, [r0, #0x40]
-	str r1, [r0, #0x44]
-	str r1, [r0, #0x48]
-	str r1, [r0, #0x4C]
-	str r1, [r0, #0x50]
-.endm /* init_aips */
-
-.macro setup_pll pll, freq
-.endm
-
-.macro init_clock
-
-/* PLL1, PLL2, and PLL3 are enabled by ROM */
-#ifdef CONFIG_PLL3
-	/* enable PLL3 for UART */
-	ldr r0, ANATOP_BASE_ADDR_W
-
-	/* power up PLL */
-	ldr r1, [r0, #ANATOP_USB1]
-	orr r1, r1, #0x1000
-	str r1, [r0, #ANATOP_USB1]
-
-	/* enable PLL */
-	ldr r1, [r0, #ANATOP_USB1]
-	orr r1, r1, #0x2000
-	str r1, [r0, #ANATOP_USB1]
-
-	/* wait PLL lock */
-100:
-	ldr r1, [r0, #ANATOP_USB1]
-	mov r1, r1, lsr #31
-	cmp r1, #0x1
-	bne 100b
-
-	/* clear bypass bit */
-	ldr r1, [r0, #ANATOP_USB1]
-	and r1, r1, #0xfffeffff
-	str r1, [r0, #ANATOP_USB1]
-#endif
-
-	/* Restore the default values in the Gate registers */
-	ldr r0, CCM_BASE_ADDR_W
-	ldr r1, =0xC0003F
-	str r1, [r0, #CLKCTL_CCGR0]
-	ldr r1, =0x30FC00
-	str r1, [r0, #CLKCTL_CCGR1]
-	ldr r1, =0xFFFC000
-	str r1, [r0, #CLKCTL_CCGR2]
-	ldr r1, =0x3FF00000
-	str r1, [r0, #CLKCTL_CCGR3]
-	ldr r1, =0xFFF300
-	str r1, [r0, #CLKCTL_CCGR4]
-	ldr r1, =0xF0000C3
-	str r1, [r0, #CLKCTL_CCGR5]
-	ldr r1, =0x3C0
-	str r1, [r0, #CLKCTL_CCGR6]
-.endm
-
-.section ".text.init", "x"
-
-.globl lowlevel_init
-lowlevel_init:
-
-	inv_dcache
-
-	init_l2cc
-
-	init_aips
-
-	init_clock
-
-	mov pc, lr
-
-/* Board level setting value */
-ANATOP_BASE_ADDR_W:		.word ANATOP_BASE_ADDR
-CCM_BASE_ADDR_W:		.word CCM_BASE_ADDR
diff --git a/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c b/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c
deleted file mode 100644
index 1c36e77..0000000
--- a/board/freescale/mx6q_sabreauto/mx6q_sabreauto.c
+++ /dev/null
@@ -1,787 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mx6.h>
-#include <asm/arch/mx6_pins.h>
-#include <asm/arch/iomux-v3.h>
-#include <asm/errno.h>
-#include <miiphy.h>
-#if defined(CONFIG_VIDEO_MX5)
-#include <linux/list.h>
-#include <linux/fb.h>
-#include <linux/mxcfb.h>
-#include <ipu.h>
-#include <lcd.h>
-#endif
-
-#if CONFIG_I2C_MXC
-#include <i2c.h>
-#endif
-
-#ifdef CONFIG_CMD_MMC
-#include <mmc.h>
-#include <fsl_esdhc.h>
-#endif
-
-#ifdef CONFIG_ARCH_MMU
-#include <asm/mmu.h>
-#include <asm/arch/mmu.h>
-#endif
-
-#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-#include <asm/imx_iim.h>
-#endif
-
-#ifdef CONFIG_CMD_CLOCK
-#include <asm/clock.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static u32 system_rev;
-static enum boot_device boot_dev;
-
-#ifdef CONFIG_VIDEO_MX5
-extern unsigned char fsl_bmp_600x400[];
-extern int fsl_bmp_600x400_size;
-extern int g_ipu_hw_rev;
-
-#if defined(CONFIG_BMP_8BPP)
-unsigned short colormap[256];
-#elif defined(CONFIG_BMP_16BPP)
-unsigned short colormap[65536];
-#else
-unsigned short colormap[16777216];
-#endif
-
-static int di = 1;
-
-extern int ipuv3_fb_init(struct fb_videomode *mode, int di,
-			int interface_pix_fmt,
-			ipu_di_clk_parent_t di_clk_parent,
-			int di_clk_val);
-
-static struct fb_videomode lvds_xga = {
-	 "XGA", 60, 1024, 768, 15385, 220, 40, 21, 7, 60, 10,
-	 FB_SYNC_EXT,
-	 FB_VMODE_NONINTERLACED,
-	 0,
-};
-
-vidinfo_t panel_info;
-#endif
-
-static inline void setup_boot_device(void)
-{
-	uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
-	uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
-	uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
-
-	switch (bt_mem_ctl) {
-	case 0x0:
-		if (bt_mem_type)
-			boot_dev = ONE_NAND_BOOT;
-		else
-			boot_dev = WEIM_NOR_BOOT;
-		break;
-	case 0x2:
-			boot_dev = SATA_BOOT;
-		break;
-	case 0x3:
-		if (bt_mem_type)
-			boot_dev = SPI_NOR_BOOT;
-		else
-			boot_dev = I2C_BOOT;
-		break;
-	case 0x4:
-	case 0x5:
-		boot_dev = SD_BOOT;
-		break;
-	case 0x6:
-	case 0x7:
-		boot_dev = MMC_BOOT;
-		break;
-	case 0x8 ... 0xf:
-		boot_dev = NAND_BOOT;
-		break;
-	default:
-		boot_dev = UNKNOWN_BOOT;
-		break;
-	}
-}
-
-enum boot_device get_boot_device(void)
-{
-	return boot_dev;
-}
-
-u32 get_board_rev(void)
-{
-
-	system_rev = 0x63000;
-
-	return system_rev;
-}
-
-#ifdef CONFIG_ARCH_MMU
-void board_mmu_init(void)
-{
-	unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
-	unsigned long i;
-
-	/*
-	* Set the TTB register
-	*/
-	asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
-
-	/*
-	* Set the Domain Access Control Register
-	*/
-	i = ARM_ACCESS_DACR_DEFAULT;
-	asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
-
-	/*
-	* First clear all TT entries - ie Set them to Faulting
-	*/
-	memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
-	/* Actual   Virtual  Size   Attributes          Function */
-	/* Base     Base     MB     cached? buffered?  access permissions */
-	/* xxx00000 xxx00000 */
-	X_ARM_MMU_SECTION(0x000, 0x000, 0x001,
-			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
-			ARM_ACCESS_PERM_RW_RW); /* ROM, 1M */
-	X_ARM_MMU_SECTION(0x001, 0x001, 0x008,
-			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
-			ARM_ACCESS_PERM_RW_RW); /* 8M */
-	X_ARM_MMU_SECTION(0x009, 0x009, 0x001,
-			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
-			ARM_ACCESS_PERM_RW_RW); /* IRAM */
-	X_ARM_MMU_SECTION(0x00A, 0x00A, 0x0F6,
-			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
-			ARM_ACCESS_PERM_RW_RW); /* 246M */
-	/* 2 GB memory starting at 0x10000000, only map 1.875 GB */
-	X_ARM_MMU_SECTION(0x100, 0x100, 0x780,
-			ARM_CACHEABLE, ARM_BUFFERABLE,
-			ARM_ACCESS_PERM_RW_RW);
-	/* uncached alias of the same 1.875 GB memory */
-	X_ARM_MMU_SECTION(0x100, 0x880, 0x780,
-			ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
-			ARM_ACCESS_PERM_RW_RW);
-
-	/* Enable MMU */
-	MMU_ON();
-}
-#endif
-
-#ifdef CONFIG_DWC_AHSATA
-
-#define ANATOP_PLL_LOCK                 0x80000000
-#define ANATOP_PLL_ENABLE_MASK          0x00002000
-#define ANATOP_PLL_BYPASS_MASK          0x00010000
-#define ANATOP_PLL_LOCK                 0x80000000
-#define ANATOP_PLL_PWDN_MASK            0x00001000
-#define ANATOP_PLL_HOLD_RING_OFF_MASK   0x00000800
-#define ANATOP_SATA_CLK_ENABLE_MASK     0x00100000
-
-int setup_sata(void)
-{
-	u32 reg = 0;
-	s32 timeout = 100000;
-
-	/* Enable sata clock */
-	reg = readl(CCM_BASE_ADDR + 0x7c); /* CCGR5 */
-	reg |= 0x30;
-	writel(reg, CCM_BASE_ADDR + 0x7c);
-
-	/* Enable PLLs */
-	reg = readl(ANATOP_BASE_ADDR + 0xe0); /* ENET PLL */
-	reg &= ~ANATOP_PLL_PWDN_MASK;
-	writel(reg, ANATOP_BASE_ADDR + 0xe0);
-	reg |= ANATOP_PLL_ENABLE_MASK;
-	while (timeout--) {
-		if (readl(ANATOP_BASE_ADDR + 0xe0) & ANATOP_PLL_LOCK)
-			break;
-	}
-	if (timeout <= 0)
-		return -1;
-	reg &= ~ANATOP_PLL_BYPASS_MASK;
-	writel(reg, ANATOP_BASE_ADDR + 0xe0);
-	reg |= ANATOP_SATA_CLK_ENABLE_MASK;
-	writel(reg, ANATOP_BASE_ADDR + 0xe0);
-
-	/* Enable sata phy */
-	reg = readl(IOMUXC_BASE_ADDR + 0x34); /* GPR13 */
-
-	reg &= ~0x07ffffff;
-	/*
-	 * rx_eq_val_0 = 5 [26:24]
-	 * los_lvl = 0x12 [23:19]
-	 * rx_dpll_mode_0 = 0x3 [18:16]
-	 * mpll_ss_en = 0x0 [14]
-	 * tx_atten_0 = 0x4 [13:11]
-	 * tx_boost_0 = 0x0 [10:7]
-	 * tx_lvl = 0x11 [6:2]
-	 * mpll_ck_off_b = 0x1 [1]
-	 * tx_edgerate_0 = 0x0 [0]
-	 * */
-	reg |= 0x59124c6;
-	writel(reg, IOMUXC_BASE_ADDR + 0x34);
-
-	return 0;
-}
-#endif
-
-int dram_init(void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-	return 0;
-}
-
-static void setup_uart(void)
-{
-	/* UART4 TXD */
-	mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL0__UART4_TXD);
-
-	/* UART4 RXD */
-	mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW0__UART4_RXD);
-}
-
-#ifdef CONFIG_VIDEO_MX5
-#ifdef CONFIG_I2C_MXC
-static void setup_i2c(unsigned int module_base)
-{
-	unsigned int reg;
-
-	switch (module_base) {
-	case I2C1_BASE_ADDR:
-		/* i2c1 SDA */
-		mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT8__I2C1_SDA);
-
-		/* i2c1 SCL */
-		mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT9__I2C1_SCL);
-
-		/* Enable i2c clock */
-		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
-		reg |= 0xC0;
-		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
-
-		break;
-	case I2C2_BASE_ADDR:
-		/* i2c2 SDA */
-		mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW3__I2C2_SDA);
-
-		/* i2c2 SCL */
-		mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL3__I2C2_SCL);
-
-		/* Enable i2c clock */
-		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
-		reg |= 0x300;
-		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
-
-		break;
-	case I2C3_BASE_ADDR:
-		/* GPIO_5 for I2C3_SCL */
-		mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_5__I2C3_SCL);
-
-		/* GPIO_16 for I2C3_SDA */
-		mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_16__I2C3_SDA);
-
-		/* Enable i2c clock */
-		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
-		reg |= 0xC00;
-		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
-
-		break;
-	default:
-		printf("Invalid I2C base: 0x%x\n", module_base);
-		break;
-	}
-}
-
-void setup_lvds_poweron(void)
-{
-	uchar value;
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
-	i2c_read(0x1f, 3, 1, &value, 1);
-	value &= ~0x2;
-	i2c_write(0x1f, 3, 1, &value, 1);
-
-	i2c_read(0x1f, 1, 1, &value, 1);
-	value |= 0x2;
-	i2c_write(0x1f, 1, 1, &value, 1);
-}
-#endif
-#endif
-
-#define HW_OCOTP_MACn(n)       (0x00000620 + (n) * 0x10)
-
-#ifdef CONFIG_MXC_FEC
-#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM
-
-int fec_get_mac_addr(unsigned char *mac)
-{
-	u32 *ocotp_mac_base =
-		(u32 *)(OCOTP_BASE_ADDR + HW_OCOTP_MACn(0));
-	int i;
-
-	for (i = 0; i < 6; ++i, ++ocotp_mac_base)
-		mac[6 - 1 - i] = readl(++ocotp_mac_base);
-	return 0;
-}
-
-#endif
-#endif
-
-#ifdef CONFIG_NET_MULTI
-int board_eth_init(bd_t *bis)
-{
-	int rc = -ENODEV;
-
-	return rc;
-}
-#endif
-
-#ifdef CONFIG_CMD_MMC
-
-/* On this board, only SD3 can support 1.8V signalling
- * that is required for UHS-I mode of operation.
- * Last element in struct is used to indicate 1.8V support.
- */
-struct fsl_esdhc_cfg usdhc_cfg[4] = {
-	{USDHC1_BASE_ADDR, 1, 1, 1, 0},
-	{USDHC2_BASE_ADDR, 1, 1, 1, 0},
-	{USDHC3_BASE_ADDR, 1, 1, 1, 1},
-	{USDHC4_BASE_ADDR, 1, 1, 1, 0},
-};
-
-#ifdef CONFIG_DYNAMIC_MMC_DEVNO
-int get_mmc_env_devno(void)
-{
-	uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
-
-	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
-	return (soc_sbmr & 0x00001800) >> 11;
-}
-#endif
-
-iomux_v3_cfg_t mx6q_usdhc1_pads[] = {
-	MX6Q_PAD_SD1_CLK__USDHC1_CLK,
-	MX6Q_PAD_SD1_CMD__USDHC1_CMD,
-	MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
-	MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
-	MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
-	MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
-};
-
-iomux_v3_cfg_t mx6q_usdhc2_pads[] = {
-	MX6Q_PAD_SD2_CLK__USDHC2_CLK,
-	MX6Q_PAD_SD2_CMD__USDHC2_CMD,
-	MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
-	MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
-	MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
-	MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
-};
-
-iomux_v3_cfg_t mx6q_usdhc3_pads[] = {
-	MX6Q_PAD_SD3_CLK__USDHC3_CLK,
-	MX6Q_PAD_SD3_CMD__USDHC3_CMD,
-	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0,
-	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1,
-	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2,
-	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3,
-	MX6Q_PAD_SD3_DAT4__USDHC3_DAT4,
-	MX6Q_PAD_SD3_DAT5__USDHC3_DAT5,
-	MX6Q_PAD_SD3_DAT6__USDHC3_DAT6,
-	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7,
-	MX6Q_PAD_GPIO_18__USDHC3_VSELECT,
-};
-
-iomux_v3_cfg_t mx6q_usdhc4_pads[] = {
-	MX6Q_PAD_SD4_CLK__USDHC4_CLK,
-	MX6Q_PAD_SD4_CMD__USDHC4_CMD,
-	MX6Q_PAD_SD4_DAT0__USDHC4_DAT0,
-	MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
-	MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
-	MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
-	MX6Q_PAD_SD4_DAT4__USDHC4_DAT4,
-	MX6Q_PAD_SD4_DAT5__USDHC4_DAT5,
-	MX6Q_PAD_SD4_DAT6__USDHC4_DAT6,
-	MX6Q_PAD_SD4_DAT7__USDHC4_DAT7,
-};
-
-int usdhc_gpio_init(bd_t *bis)
-{
-	s32 status = 0;
-	u32 index = 0;
-
-	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM;
-		++index) {
-		switch (index) {
-		case 0:
-			mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc1_pads,
-				sizeof(mx6q_usdhc1_pads) / sizeof(mx6q_usdhc1_pads[0]));
-			break;
-		case 1:
-			mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc2_pads,
-				sizeof(mx6q_usdhc2_pads) / sizeof(mx6q_usdhc2_pads[0]));
-			break;
-		case 2:
-			mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc3_pads,
-				sizeof(mx6q_usdhc3_pads) / sizeof(mx6q_usdhc3_pads[0]));
-			break;
-		case 3:
-			mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc4_pads,
-				sizeof(mx6q_usdhc4_pads) / sizeof(mx6q_usdhc4_pads[0]));
-			break;
-		default:
-			printf("Warning: you configured more USDHC controllers"
-				"(%d) then supported by the board (%d)\n",
-				index+1, CONFIG_SYS_FSL_USDHC_NUM);
-			return status;
-		}
-		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
-	}
-
-	return status;
-}
-
-int board_mmc_init(bd_t *bis)
-{
-	if (!usdhc_gpio_init(bis))
-		return 0;
-	else
-		return -1;
-}
-
-/* For DDR mode operation, provide target delay parameter for each SD port.
- * Use cfg->esdhc_base to distinguish the SD port #. The delay for each port
- * is dependent on signal layout for that particular port.  If the following
- * CONFIG is not defined, then the default target delay value will be used.
- */
-#ifdef CONFIG_GET_DDR_TARGET_DELAY
-u32 get_ddr_delay(struct fsl_esdhc_cfg *cfg)
-{
-	/* No delay required on SABRE Auto board SD ports */
-	return 0;
-}
-#endif
-
-#endif
-
-#ifdef CONFIG_LCD
-void lcd_enable(void)
-{
-	char *s;
-	int ret;
-	unsigned int reg;
-
-	s = getenv("lvds_num");
-	di = simple_strtol(s, NULL, 10);
-
-	/*
-	* hw_rev 2: IPUV3DEX
-	* hw_rev 3: IPUV3M
-	* hw_rev 4: IPUV3H
-	*/
-	g_ipu_hw_rev = IPUV3_HW_REV_IPUV3H;
-
-	/* set GPIO_9 to high so that backlight control could be high */
-	mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_9__GPIO_1_9);
-	reg = readl(GPIO1_BASE_ADDR + GPIO_GDIR);
-	reg |= (1 << 9);
-	writel(reg, GPIO1_BASE_ADDR + GPIO_GDIR);
-
-	reg = readl(GPIO1_BASE_ADDR + GPIO_DR);
-	reg |= (1 << 9);
-	writel(reg, GPIO1_BASE_ADDR + GPIO_DR);
-
-	/* Enable IPU clock */
-	if (di == 1) {
-		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3);
-		reg |= 0xC033;
-		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3);
-	} else {
-		reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR3);
-		reg |= 0x300F;
-		writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR3);
-	}
-
-	ret = ipuv3_fb_init(&lvds_xga, di, IPU_PIX_FMT_RGB666,
-			DI_PCLK_LDB, 65000000);
-	if (ret)
-		puts("LCD cannot be configured\n");
-
-	reg = readl(ANATOP_BASE_ADDR + 0xF0);
-	reg &= ~0x00003F00;
-	reg |= 0x00001300;
-	writel(reg, ANATOP_BASE_ADDR + 0xF4);
-
-	reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR);
-	reg &= ~0x00007E00;
-	reg |= 0x00003600;
-	writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR);
-
-	reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR2);
-	reg |= 0x00000C00;
-	writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR2);
-
-	reg = 0x0002A953;
-	writel(reg, CCM_BASE_ADDR + CLKCTL_CHSCCDR);
-
-	if (di == 1)
-		writel(0x40C, IOMUXC_BASE_ADDR + 0x8);
-	else
-		writel(0x201, IOMUXC_BASE_ADDR + 0x8);
-}
-#endif
-
-#ifdef CONFIG_VIDEO_MX5
-void panel_info_init(void)
-{
-	panel_info.vl_bpix = LCD_BPP;
-	panel_info.vl_col = lvds_xga.xres;
-	panel_info.vl_row = lvds_xga.yres;
-	panel_info.cmap = colormap;
-}
-#endif
-
-#ifdef CONFIG_SPLASH_SCREEN
-void setup_splash_image(void)
-{
-	char *s;
-	ulong addr;
-
-	s = getenv("splashimage");
-
-	if (s != NULL) {
-		addr = simple_strtoul(s, NULL, 16);
-
-#if defined(CONFIG_ARCH_MMU)
-		addr = ioremap_nocache(iomem_to_phys(addr),
-				fsl_bmp_600x400_size);
-#endif
-		memcpy((char *)addr, (char *)fsl_bmp_600x400,
-				fsl_bmp_600x400_size);
-	}
-}
-#endif
-
-int board_init(void)
-{
-#ifdef CONFIG_MFG
-/* MFG firmware need reset usb to avoid host crash firstly */
-#define USBCMD 0x140
-	int val = readl(OTG_BASE_ADDR + USBCMD);
-	val &= ~0x1; /*RS bit*/
-	writel(val, OTG_BASE_ADDR + USBCMD);
-#endif
-	mxc_iomux_v3_init((void *)IOMUXC_BASE_ADDR);
-	setup_boot_device();
-
-	/* board id for linux */
-	gd->bd->bi_arch_number = MACH_TYPE_MX6Q_SABREAUTO;
-
-	/* address of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	setup_uart();
-
-#ifdef CONFIG_DWC_AHSATA
-	setup_sata();
-#endif
-
-#ifdef CONFIG_VIDEO_MX5
-
-#ifdef CONFIG_I2C_MXC
-	setup_i2c(CONFIG_SYS_I2C_PORT);
-	/* Enable lvds power */
-	setup_lvds_poweron();
-#endif
-
-	panel_info_init();
-
-	gd->fb_base = CONFIG_FB_BASE;
-#ifdef CONFIG_ARCH_MMU
-	gd->fb_base = ioremap_nocache(iomem_to_phys(gd->fb_base), 0);
-#endif
-#endif
-
-	return 0;
-}
-
-int board_late_init(void)
-{
-	return 0;
-}
-
-static int phy_read(char *devname, unsigned char addr, unsigned char reg,
-		    unsigned short *pdata)
-{
-	int ret = miiphy_read(devname, addr, reg, pdata);
-	if (ret)
-		printf("Error reading from %s PHY addr=%02x reg=%02x\n",
-		       devname, addr, reg);
-	return ret;
-}
-
-static int phy_write(char *devname, unsigned char addr, unsigned char reg,
-		     unsigned short value)
-{
-	int ret = miiphy_write(devname, addr, reg, value);
-	if (ret)
-		printf("Error writing to %s PHY addr=%02x reg=%02x\n", devname,
-		       addr, reg);
-	return ret;
-}
-
-int mx6_rgmii_rework(char *devname, int phy_addr)
-{
-	unsigned short val;
-
-	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
-	phy_write(devname, phy_addr, 0xd, 0x7);
-	phy_write(devname, phy_addr, 0xe, 0x8016);
-	phy_write(devname, phy_addr, 0xd, 0x4007);
-	phy_read(devname, phy_addr, 0xe, &val);
-
-	val &= 0xffe3;
-	val |= 0x18;
-	phy_write(devname, phy_addr, 0xe, val);
-
-	/* introduce tx clock delay */
-	phy_write(devname, phy_addr, 0x1d, 0x5);
-	phy_read(devname, phy_addr, 0x1e, &val);
-	val |= 0x0100;
-	phy_write(devname, phy_addr, 0x1e, val);
-
-	return 0;
-}
-
-iomux_v3_cfg_t enet_pads[] = {
-	MX6Q_PAD_KEY_COL1__ENET_MDIO,
-	MX6Q_PAD_KEY_COL2__ENET_MDC,
-	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
-	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
-	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
-	MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
-	MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
-	MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
-	MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
-	MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
-	MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
-	MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
-	MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
-	MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
-	MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
-	MX6Q_PAD_GPIO_0__CCM_CLKO,
-	MX6Q_PAD_GPIO_3__CCM_CLKO2,
-};
-
-void enet_board_init(void)
-{
-	unsigned int reg;
-	iomux_v3_cfg_t enet_reset =
-			(MX6Q_PAD_KEY_ROW4__GPIO_4_15 &
-			~MUX_PAD_CTRL_MASK)           |
-			 MUX_PAD_CTRL(0x84);
-
-	mxc_iomux_v3_setup_multiple_pads(enet_pads,
-			ARRAY_SIZE(enet_pads));
-
-	mxc_iomux_v3_setup_pad(enet_reset);
-
-	/* phy reset: gpio4-15 */
-	reg = readl(GPIO4_BASE_ADDR + 0x0);
-	reg &= ~0x8000;
-	writel(reg, GPIO4_BASE_ADDR + 0x0);
-
-	reg = readl(GPIO4_BASE_ADDR + 0x4);
-	reg |= 0x8000;
-	writel(reg, GPIO4_BASE_ADDR + 0x4);
-
-	udelay(500);
-
-	reg = readl(GPIO4_BASE_ADDR + 0x0);
-	reg |= 0x8000;
-	writel(reg, GPIO4_BASE_ADDR + 0x0);
-}
-
-int checkboard(void)
-{
-	printf("Board: MX6Q-SABREAUTO:[ ");
-
-	switch (__REG(SRC_BASE_ADDR + 0x8)) {
-	case 0x0001:
-		printf("POR");
-		break;
-	case 0x0009:
-		printf("RST");
-		break;
-	case 0x0010:
-	case 0x0011:
-		printf("WDOG");
-		break;
-	default:
-		printf("unknown");
-	}
-	printf("]\n");
-
-	printf("Boot Device: ");
-	switch (get_boot_device()) {
-	case WEIM_NOR_BOOT:
-		printf("NOR\n");
-		break;
-	case ONE_NAND_BOOT:
-		printf("ONE NAND\n");
-		break;
-	case PATA_BOOT:
-		printf("PATA\n");
-		break;
-	case SATA_BOOT:
-		printf("SATA\n");
-		break;
-	case I2C_BOOT:
-		printf("I2C\n");
-		break;
-	case SPI_NOR_BOOT:
-		printf("SPI NOR\n");
-		break;
-	case SD_BOOT:
-		printf("SD\n");
-		break;
-	case MMC_BOOT:
-		printf("MMC\n");
-		break;
-	case NAND_BOOT:
-		printf("NAND\n");
-		break;
-	case UNKNOWN_BOOT:
-	default:
-		printf("UNKNOWN\n");
-		break;
-	}
-	return 0;
-}
diff --git a/board/freescale/mx6q_sabreauto/u-boot.lds b/board/freescale/mx6q_sabreauto/u-boot.lds
deleted file mode 100644
index f3ebb48..0000000
--- a/board/freescale/mx6q_sabreauto/u-boot.lds
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2011 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-	. = 0x00000000;
-
-	. = ALIGN(4);
-	.text	   :
-	{
-	  /* WARNING - the following is hand-optimized to fit within	*/
-	  /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-	  board/freescale/mx6q_sabreauto/flash_header.o	(.text.flasheader)
-	  cpu/arm_cortexa8/start.o
-	  board/freescale/mx6q_sabreauto/libmx6q_sabreauto.a	(.text)
-	  lib_arm/libarm.a		(.text)
-	  net/libnet.a			(.text)
-	  drivers/mtd/libmtd.a		(.text)
-	  drivers/mmc/libmmc.a		(.text)
-
-	  . = DEFINED(env_offset) ? env_offset : .;
-	  common/env_embedded.o(.text)
-
-	  *(.text)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(.rodata) }
-
-	. = ALIGN(4);
-	.data : { *(.data) }
-
-	. = ALIGN(4);
-	.got : { *(.got) }
-
-	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-
-	. = ALIGN(4);
-	_end_of_copy = .; /* end_of ROM copy code here */
-	__bss_start = .;
-	.bss : { *(.bss) }
-	_end = .;
-}