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| author | Huang Shijie <b32955@freescale.com> | 2011-10-13 17:14:08 +0800 |
|---|---|---|
| committer | Huang Shijie <b32955@freescale.com> | 2011-10-14 15:46:47 +0800 |
| commit | 856b3602d1f175706ceb54df4388e406bd3c6ff5 (patch) | |
| tree | 35a14b3cd559cff481b6107851ccab2e6135d3a0 /board/freescale/mx6q_sabreauto | |
| parent | b0d0b2e76761d6fec5c3514e6b4f8a5944b07c18 (diff) | |
| download | u-boot-imx-856b3602d1f175706ceb54df4388e406bd3c6ff5.zip u-boot-imx-856b3602d1f175706ceb54df4388e406bd3c6ff5.tar.gz u-boot-imx-856b3602d1f175706ceb54df4388e406bd3c6ff5.tar.bz2 | |
ENGR00139279-3 MX6Q: invalidate the D-CACHE
The USB boot mode does not invalidate the D-CACHE,
so the uboot will DEAD when it tries to invalidate the random data in
the cache line.
The MMC boot will do the MMU init which will do the D-CACHE invalidation.
So the MMC boot will ok in the boot procedure.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Diffstat (limited to 'board/freescale/mx6q_sabreauto')
| -rw-r--r-- | board/freescale/mx6q_sabreauto/lowlevel_init.S | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/board/freescale/mx6q_sabreauto/lowlevel_init.S b/board/freescale/mx6q_sabreauto/lowlevel_init.S index 5da8199..2ac77b9 100644 --- a/board/freescale/mx6q_sabreauto/lowlevel_init.S +++ b/board/freescale/mx6q_sabreauto/lowlevel_init.S @@ -31,6 +31,41 @@ str r0, [r1, #0x100] .endm /* init_l2cc */ +/* invalidate the D-CACHE */ +.macro inv_dcache + mov r0,#0 + mcr p15,2,r0,c0,c0,0 /* cache size selection register, select dcache */ + mrc p15,1,r0,c0,c0,0 /* cache size ID register */ + mov r0,r0,ASR #13 + ldr r3,=0xfff + and r0,r0,r3 + cmp r0,#0x7f + moveq r6,#0x1000 + beq size_done + cmp r0,#0xff + moveq r6,#0x2000 + movne r6,#0x4000 + +size_done: + mov r2,#0 + mov r3,#0x40000000 + mov r4,#0x80000000 + mov r5,#0xc0000000 + +d_inv_loop: + mcr p15,0,r2,c7,c6,2 /* invalidate dcache by set / way */ + mcr p15,0,r3,c7,c6,2 /* invalidate dcache by set / way */ + mcr p15,0,r4,c7,c6,2 /* invalidate dcache by set / way */ + mcr p15,0,r5,c7,c6,2 /* invalidate dcache by set / way */ + add r2,r2,#0x20 + add r3,r3,#0x20 + add r4,r4,#0x20 + add r5,r5,#0x20 + + cmp r2,r6 + bne d_inv_loop +.endm + /* AIPS setup - Only setup MPROTx registers. * The PACR default values are good.*/ .macro init_aips @@ -117,6 +152,8 @@ .globl lowlevel_init lowlevel_init: + inv_dcache + init_l2cc init_aips |