ENGR00159696 [MX6]Enable lpddr2 board

And new config to enable lpddr2 board with
H9TKNNN4KDMPQR-NDM chip.

Signed-off-by: Anson Huang <b20788@freescale.com>

1 files changed, 169 insertions, 0 deletions

diff --git a/board/freescale/mx6q_sabreauto/flash_header.S b/board/freescale/mx6q_sabreauto/flash_header.S
index d18ab74..4a20fb4 100644
--- a/board/freescale/mx6q_sabreauto/flash_header.S
+++ b/board/freescale/mx6q_sabreauto/flash_header.S
@@ -53,6 +53,174 @@ boot_data:        .word TEXT_BASE
 image_len:        .word _end_of_copy  - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET
 plugin:           .word 0x0
 
+#ifdef CONFIG_LPDDR2
+
+dcd_hdr:          .word 0x40e803D2 /* Tag=0xD2, Len=124*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd:    .word 0x04e403CC /* Tag=0xCC, Len=124*8 + 4, Param=0x04 */
+
+/* DCD */
+MXC_DCD_ITEM(1, CCM_BASE_ADDR + 0x18, 0x60324)
+
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x5a8, 0x00003038)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x5b0, 0x00003038)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x524, 0x00003038)
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x51c, 0x00003038)
+
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x518, 0x00003038)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x50c, 0x00003038)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x5b8, 0x00003038)
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x5c0, 0x00003038)
+
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x5ac, 0x00000038)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x5b4, 0x00000038)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x528, 0x00000038)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x520, 0x00000038)
+
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x514, 0x00000038)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x510, 0x00000038)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5bc, 0x00000038)
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5c4, 0x00000038)
+
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x56c, 0x00000038)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x578, 0x00000038)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x588, 0x00000038)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x594, 0x00000038)
+
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x57c, 0x00000038)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x590, 0x00000038)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x598, 0x00000038)
+MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
+
+MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x59c, 0x00000038)
+MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x5a0, 0x00000038)
+MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x784, 0x00000038)
+MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x788, 0x00000038)
+
+MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x794, 0x00000038)
+MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x79c, 0x00000038)
+MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x7a0, 0x00000038)
+MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x7a4, 0x00000038)
+
+MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x7a8, 0x00000038)
+MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x748, 0x00000038)
+MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x74c, 0x00000038)
+MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
+
+MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
+MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
+MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x78c, 0x00000038)
+MXC_DCD_ITEM(41, IOMUXC_BASE_ADDR + 0x798, 0x00080000)
+
+MXC_DCD_ITEM(42, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
+MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x01c, 0x00008000)
+
+MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x85c, 0x1b5f01ff)
+MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x85c, 0x1b5f01ff)
+
+MXC_DCD_ITEM(46, MMDC_P0_BASE_ADDR + 0x800, 0xa1390000)
+MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x800, 0xa1390000)
+
+MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x890, 0x00400000)
+MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x890, 0x00400000)
+
+MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x8bc, 0x00055555)
+
+MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
+MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
+
+MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
+MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
+MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
+MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
+MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
+
+MXC_DCD_ITEM(61, MMDC_P0_BASE_ADDR + 0x82c, 0xf3333333)
+MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x830, 0xf3333333)
+MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x834, 0xf3333333)
+MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x838, 0xf3333333)
+MXC_DCD_ITEM(65, MMDC_P1_BASE_ADDR + 0x82c, 0xf3333333)
+MXC_DCD_ITEM(66, MMDC_P1_BASE_ADDR + 0x830, 0xf3333333)
+MXC_DCD_ITEM(67, MMDC_P1_BASE_ADDR + 0x834, 0xf3333333)
+MXC_DCD_ITEM(68, MMDC_P1_BASE_ADDR + 0x838, 0xf3333333)
+
+MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x848, 0x49383b39)
+MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x850, 0x30364738)
+MXC_DCD_ITEM(71, MMDC_P1_BASE_ADDR + 0x848, 0x3e3c3846)
+MXC_DCD_ITEM(72, MMDC_P1_BASE_ADDR + 0x850, 0x4c294b35)
+
+MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x83c, 0x20000000)
+MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x840, 0x0)
+MXC_DCD_ITEM(75, MMDC_P1_BASE_ADDR + 0x83c, 0x20000000)
+MXC_DCD_ITEM(76, MMDC_P1_BASE_ADDR + 0x840, 0x0)
+
+MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x858, 0xf00)
+MXC_DCD_ITEM(78, MMDC_P1_BASE_ADDR + 0x858, 0xf00)
+
+MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
+MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
+
+MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0xc, 0x555a61a5)
+MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x4, 0x20036)
+MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x10, 0x160e83)
+MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x14, 0xdd)
+MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x18, 0x8174c)
+MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x2c, 0xf9f26d2)
+MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x30, 0x20e)
+MXC_DCD_ITEM(88, MMDC_P0_BASE_ADDR + 0x38, 0x200aac)
+MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x8, 0x0)
+
+MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x40, 0x5f)
+
+MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x0, 0xc3010000)
+
+MXC_DCD_ITEM(92, MMDC_P1_BASE_ADDR + 0xc, 0x555a61a5)
+MXC_DCD_ITEM(93, MMDC_P1_BASE_ADDR + 0x4, 0x20036)
+MXC_DCD_ITEM(94, MMDC_P1_BASE_ADDR + 0x10, 0x160e83)
+MXC_DCD_ITEM(95, MMDC_P1_BASE_ADDR + 0x14, 0xdd)
+MXC_DCD_ITEM(96, MMDC_P1_BASE_ADDR + 0x18, 0x8174c)
+MXC_DCD_ITEM(97, MMDC_P1_BASE_ADDR + 0x2c, 0xf9f26d2)
+MXC_DCD_ITEM(98, MMDC_P1_BASE_ADDR + 0x30, 0x20e)
+MXC_DCD_ITEM(99, MMDC_P1_BASE_ADDR + 0x38, 0x200aac)
+MXC_DCD_ITEM(100, MMDC_P1_BASE_ADDR + 0x8, 0x0)
+
+MXC_DCD_ITEM(101, MMDC_P1_BASE_ADDR + 0x40, 0x3f)
+MXC_DCD_ITEM(102, MMDC_P1_BASE_ADDR + 0x0, 0xc3010000)
+
+MXC_DCD_ITEM(103, MMDC_P0_BASE_ADDR + 0x1c, 0x3f8030)
+MXC_DCD_ITEM(104, MMDC_P0_BASE_ADDR + 0x1c, 0xff0a8030)
+MXC_DCD_ITEM(105, MMDC_P0_BASE_ADDR + 0x1c, 0xc2018030)
+MXC_DCD_ITEM(106, MMDC_P0_BASE_ADDR + 0x1c, 0x6028030)
+MXC_DCD_ITEM(107, MMDC_P0_BASE_ADDR + 0x1c, 0x2038030)
+
+MXC_DCD_ITEM(108, MMDC_P1_BASE_ADDR + 0x1c, 0x3f8030)
+MXC_DCD_ITEM(109, MMDC_P1_BASE_ADDR + 0x1c, 0xff0a8030)
+MXC_DCD_ITEM(110, MMDC_P1_BASE_ADDR + 0x1c, 0xc2018030)
+MXC_DCD_ITEM(111, MMDC_P1_BASE_ADDR + 0x1c, 0x6028030)
+MXC_DCD_ITEM(112, MMDC_P1_BASE_ADDR + 0x1c, 0x2038030)
+
+MXC_DCD_ITEM(113, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
+MXC_DCD_ITEM(114, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
+
+MXC_DCD_ITEM(115, MMDC_P0_BASE_ADDR + 0x20, 0x7800)
+MXC_DCD_ITEM(116, MMDC_P1_BASE_ADDR + 0x20, 0x7800)
+
+MXC_DCD_ITEM(117, MMDC_P0_BASE_ADDR + 0x818, 0x0)
+MXC_DCD_ITEM(118, MMDC_P1_BASE_ADDR + 0x818, 0x0)
+
+MXC_DCD_ITEM(119, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003)
+MXC_DCD_ITEM(120, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003)
+
+MXC_DCD_ITEM(121, MMDC_P0_BASE_ADDR + 0x8b8, 0x800)
+MXC_DCD_ITEM(122, MMDC_P1_BASE_ADDR + 0x8b8, 0x800)
+
+MXC_DCD_ITEM(123, MMDC_P0_BASE_ADDR + 0x1c, 0x0)
+MXC_DCD_ITEM(124, MMDC_P1_BASE_ADDR + 0x1c, 0x0)
+
+#else
+
 dcd_hdr:          .word 0x40F002D2 /* Tag=0xD2, Len=93*8 + 4 + 4, Ver=0x40 */
 write_dcd_cmd:    .word 0x04EC02CC /* Tag=0xCC, Len=93*8 + 4, Param=0x04 */
 
@@ -175,5 +343,6 @@ MXC_DCD_ITEM(91, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff)
 /* set IPU Qos=0x7 */
 MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x018, 0x00070007)
 MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x01c, 0x00070007)
+#endif
 
 #endif