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| author | Fabio Estevam <festevam@gmail.com> | 2011-08-19 03:28:10 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-09-04 11:36:11 +0200 |
| commit | 9691c5b96d889b1d4c8908c449b47d80699dc915 (patch) | |
| tree | 9e1476e7354da652274b1f7b95fbed7c59ce766c /board/freescale/mx53loco/imximage.cfg | |
| parent | 9db1bfa110ac411ab3468e817f7f74b2439eb8c8 (diff) | |
| download | u-boot-imx-9691c5b96d889b1d4c8908c449b47d80699dc915.zip u-boot-imx-9691c5b96d889b1d4c8908c449b47d80699dc915.tar.gz u-boot-imx-9691c5b96d889b1d4c8908c449b47d80699dc915.tar.bz2 | |
mx53: ddr3: Update DD3 initialization
Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011:
-change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz)
-change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from
"0x092080b0". This changes write recovery from 8 clocks to 6 clocks
(in line with ESDCFG1[tWR])
Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'board/freescale/mx53loco/imximage.cfg')
| -rw-r--r-- | board/freescale/mx53loco/imximage.cfg | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg index ce9c8fc..f30258e 100644 --- a/board/freescale/mx53loco/imximage.cfg +++ b/board/freescale/mx53loco/imximage.cfg @@ -83,14 +83,14 @@ DATA 4 0x63fd9004 0x0002002d DATA 4 0x63fd901c 0x00008032 DATA 4 0x63fd901c 0x00008033 DATA 4 0x63fd901c 0x00028031 -DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x052080b0 DATA 4 0x63fd901c 0x04008040 DATA 4 0x63fd901c 0x0000803a DATA 4 0x63fd901c 0x0000803b DATA 4 0x63fd901c 0x00028039 -DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x05208138 DATA 4 0x63fd901c 0x04008048 -DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9020 0x00005800 DATA 4 0x63fd9040 0x04b80003 DATA 4 0x63fd9058 0x00022227 DATA 4 0x63fd901c 0x00000000 |