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| author | Michal Sojka <sojka@merica.cz> | 2015-02-17 17:08:37 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-03-05 20:49:42 -0500 |
| commit | d8af39337ea82403fb54a9d345d2e47fac4a8460 (patch) | |
| tree | 84ed2f04b4c4f0dd8932be015f98dbfedd92476b /board/freescale/mx53evk | |
| parent | 22b7509efb35d7bda05260d5730124dbdc3ea9dc (diff) | |
| download | u-boot-imx-d8af39337ea82403fb54a9d345d2e47fac4a8460.zip u-boot-imx-d8af39337ea82403fb54a9d345d2e47fac4a8460.tar.gz u-boot-imx-d8af39337ea82403fb54a9d345d2e47fac4a8460.tar.bz2 | |
mtd: nand: omap_gpmc: Make ready/busy pins configurable
Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of
WAIT0 pin for determining whether the NAND is ready or not. This only
works if all NAND chips are connected to WAIT0. If some chips are
connected to the other available pin WAIT1, nand_wait() does not really
wait and prints a WARN_ON message.
This patch allows the board to provide configuration of which chip is
connected to which WAITx signal. For example, one can define in
include/configs/foo.h:
#define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1
This would mean that chips using to CS0 and 1 are connected to WAIT0 and
chips with CS2 and 3 are connected to WAIT1.
Signed-off-by: Michal Sojka <sojka@merica.cz>
Acked-by: Stefan Roese <sr@denx.de>
Tested-by: Michal Vokáč <michal.vokac@comap.cz>
Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'board/freescale/mx53evk')
0 files changed, 0 insertions, 0 deletions