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| author | Ye Li <ye.li@nxp.com> | 2016-07-28 11:42:14 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 14:04:43 +0800 |
| commit | 70bc3dd2c40a5c5479b4aae6037e7914061a524e (patch) | |
| tree | 9ca778dac58ecc6f88efc72ea3a35393fbf70d7d /board/freescale/mx53ard | |
| parent | 4976f8f1adc5518135f663ef33991151be9d5067 (diff) | |
| download | u-boot-imx-70bc3dd2c40a5c5479b4aae6037e7914061a524e.zip u-boot-imx-70bc3dd2c40a5c5479b4aae6037e7914061a524e.tar.gz u-boot-imx-70bc3dd2c40a5c5479b4aae6037e7914061a524e.tar.bz2 | |
MLK-12996 imx: mx6dqp/dq: Fix SATA read/write fail after booting from SATA
We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET
ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before
this changing, SATA read/write can't work after it. And we have to re-init SATA.
The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing.
This patch is an work around that moves the ENET clock setting
(enable_fec_anatop_clock) from ethernet init to board_init which is prior
than SATA initialization. So there is no PLL6 change after SATA init.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit fd8fbf7fa0b10199ac89cd13cae851149f51accb)
Diffstat (limited to 'board/freescale/mx53ard')
0 files changed, 0 insertions, 0 deletions