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authorLily Zhang <r58066@freescale.com>2011-01-14 23:42:22 +0800
committerLily Zhang <r58066@freescale.com>2011-01-15 00:01:19 +0800
commite6ed124f273d9439f03a32bcdea064574c32c1d2 (patch)
treebb55460763ab45c68498367f4873d5b1d5f0cb35 /board/freescale/mx53_smd
parent0217e541efbcd63136ce6300f55515d454387751 (diff)
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ENGR00137552 MX53: increase VDDGP as 1.2V for 1GHZ
The norminal voltage of VDDGP for 1GHZ is 1.2V in MX53 TO2.0 datasheet (RevD). So set the CPU frequency as 800MHZ firstly since VDDGP is 1.1V after power on. After increasing VDDGP as 1.2V, increase CPU as 1GHZ. Signed-off-by: Lily Zhang <r58066@freescale.com>
Diffstat (limited to 'board/freescale/mx53_smd')
-rw-r--r--board/freescale/mx53_smd/lowlevel_init.S2
-rw-r--r--board/freescale/mx53_smd/mx53_smd.c14
2 files changed, 15 insertions, 1 deletions
diff --git a/board/freescale/mx53_smd/lowlevel_init.S b/board/freescale/mx53_smd/lowlevel_init.S
index 5feaaf1..60ee843 100644
--- a/board/freescale/mx53_smd/lowlevel_init.S
+++ b/board/freescale/mx53_smd/lowlevel_init.S
@@ -97,7 +97,7 @@
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
- setup_pll PLL1_BASE_ADDR, 1000
+ setup_pll PLL1_BASE_ADDR, 800
setup_pll PLL3_BASE_ADDR, 400
diff --git a/board/freescale/mx53_smd/mx53_smd.c b/board/freescale/mx53_smd/mx53_smd.c
index be1185f..1b44b3c 100644
--- a/board/freescale/mx53_smd/mx53_smd.c
+++ b/board/freescale/mx53_smd/mx53_smd.c
@@ -363,6 +363,16 @@ static void setup_i2c(unsigned int module_base)
break;
}
}
+
+void setup_pmic_voltages(void)
+{
+ int value;
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ /* increase VDDGP as 1.2V for 1GHZ */
+ value = 0x5c;
+ i2c_write(0x48, 0x2e, 1, &value, 1);
+}
+
#endif
#if defined(CONFIG_DWC_AHSATA)
@@ -684,6 +694,10 @@ int board_init(void)
#ifdef CONFIG_I2C_MXC
setup_i2c(CONFIG_SYS_I2C_PORT);
+ /* Increase VDDGP voltage */
+ setup_pmic_voltages();
+ /* Switch to 1GHZ */
+ clk_config(CONFIG_REF_CLK_FREQ, 1000, CPU_CLK);
#endif
#if defined(CONFIG_DWC_AHSATA)