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| author | Jason Chen <b02280@freescale.com> | 2011-03-31 15:30:23 +0800 |
|---|---|---|
| committer | Jason Chen <b02280@freescale.com> | 2011-03-31 15:30:23 +0800 |
| commit | 0f165488b255c8243284e1fbf6ebd74f2795dd0a (patch) | |
| tree | 25e2fe1d169f70a87336ce9ebc6d9f5645c6b0af /board/freescale/mx53_smd | |
| parent | 068bed0069dfe66bf01cc72fc4e41a32b2cb94d4 (diff) | |
| download | u-boot-imx-0f165488b255c8243284e1fbf6ebd74f2795dd0a.zip u-boot-imx-0f165488b255c8243284e1fbf6ebd74f2795dd0a.tar.gz u-boot-imx-0f165488b255c8243284e1fbf6ebd74f2795dd0a.tar.bz2 | |
ENGR00141363: change mx53 uart clk parent to pll2
Change all mx53 platform uart clk default parent to pll2.
MX53 SMD board need support LVDS and HDMI at the same time, they
may use the same clock parent-pll4, so kernel need change ipu di
clock parent to pll3, after that, uart clock parent need change
to pll2 to avoid console mess.
Signed-off-by: Jason Chen <b02280@freescale.com>
Diffstat (limited to 'board/freescale/mx53_smd')
| -rw-r--r-- | board/freescale/mx53_smd/lowlevel_init.S | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/board/freescale/mx53_smd/lowlevel_init.S b/board/freescale/mx53_smd/lowlevel_init.S index 60ee843..07af735 100644 --- a/board/freescale/mx53_smd/lowlevel_init.S +++ b/board/freescale/mx53_smd/lowlevel_init.S @@ -126,6 +126,12 @@ ldr r1, CCM_VAL_0x00016154 str r1, [r0, #CLKCTL_CBCMR] + /*change uart clk parent to pll2*/ + ldr r1, [r0, #CLKCTL_CSCMR1] + and r1, r1, #0xfcffffff + orr r1, r1, #0x01000000 + str r1, [r0, #CLKCTL_CSCMR1] + /* make sure change is effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 @@ -148,10 +154,10 @@ mov r1, #0x0 str r1, [r0, #CLKCTL_CCSR] + /* make uart div=6*/ ldr r1, [r0, #CLKCTL_CSCDR1] - orr r1, r1, #0x3f - eor r1, r1, #0x3f - orr r1, r1, #0x21 + and r1, r1, #0xffffffc0 + orr r1, r1, #0x0a str r1, [r0, #CLKCTL_CSCDR1] /* Restore the default values in the Gate registers */ |