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| author | Terry Lv <r65388@freescale.com> | 2011-05-30 15:41:21 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2011-06-09 15:36:38 +0800 |
| commit | 4a4da8081f15c0c100822837a1f9290384f1713e (patch) | |
| tree | eba9cc210243a06c05bcfe9c8a8722c2854a35f1 /board/freescale/mx53_loco | |
| parent | 13d0cc1e7598fe14fa4e6a0b0b5bbdc7aa0b98e2 (diff) | |
| download | u-boot-imx-4a4da8081f15c0c100822837a1f9290384f1713e.zip u-boot-imx-4a4da8081f15c0c100822837a1f9290384f1713e.tar.gz u-boot-imx-4a4da8081f15c0c100822837a1f9290384f1713e.tar.bz2 | |
ENGR00144224: MX53: Add MMU mapping for all peripherals
Not all peripherals are mapped in MMU.
Thus we add those missed mapped area.
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'board/freescale/mx53_loco')
| -rw-r--r-- | board/freescale/mx53_loco/mx53_loco.c | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/board/freescale/mx53_loco/mx53_loco.c b/board/freescale/mx53_loco/mx53_loco.c index e77230f..5a5e820 100644 --- a/board/freescale/mx53_loco/mx53_loco.c +++ b/board/freescale/mx53_loco/mx53_loco.c @@ -173,16 +173,25 @@ void board_mmu_init(void) /* Actual Virtual Size Attributes Function */ /* Base Base MB cached? buffered? access permissions */ /* xxx00000 xxx00000 */ - X_ARM_MMU_SECTION(0x000, 0x000, 0x10, + X_ARM_MMU_SECTION(0x000, 0x000, 0x010, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM, 16M */ + X_ARM_MMU_SECTION(0x010, 0x010, 0x060, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* Reserved, 96M */ X_ARM_MMU_SECTION(0x070, 0x070, 0x010, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, - ARM_ACCESS_PERM_RW_RW); /* IRAM */ + ARM_ACCESS_PERM_RW_RW); /* IRAM, 16M */ + X_ARM_MMU_SECTION(0x080, 0x080, 0x080, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* Reserved region + TZIC. 1M */ X_ARM_MMU_SECTION(0x100, 0x100, 0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SATA */ - X_ARM_MMU_SECTION(0x180, 0x180, 0x100, + X_ARM_MMU_SECTION(0x140, 0x140, 0x040, + ARM_UNCACHEABLE, ARM_UNBUFFERABLE, + ARM_ACCESS_PERM_RW_RW); /* Reserved, 64M */ + X_ARM_MMU_SECTION(0x180, 0x180, 0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3M */ X_ARM_MMU_SECTION(0x200, 0x200, 0x200, @@ -203,15 +212,15 @@ void board_mmu_init(void) X_ARM_MMU_SECTION(0xB00, 0xD00, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSD0 512M */ - X_ARM_MMU_SECTION(0xF00, 0xF00, 0x100, + X_ARM_MMU_SECTION(0xF00, 0xF00, 0x07F, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/ - X_ARM_MMU_SECTION(0xF7F, 0xF7F, 0x040, + X_ARM_MMU_SECTION(0xF7F, 0xF7F, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* NAND Flash buffer */ - X_ARM_MMU_SECTION(0xF80, 0xF80, 0x001, + X_ARM_MMU_SECTION(0xF80, 0xF80, 0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, - ARM_ACCESS_PERM_RW_RW); /* iRam */ + ARM_ACCESS_PERM_RW_RW); /* iRam + GPU3D + Reserved */ /* Workaround for arm errata #709718 */ /* Setup PRRR so device is always mapped to non-shared */ |