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authorTerry Lv <r65388@freescale.com>2011-08-24 16:15:47 +0800
committerTerry Lv <r65388@freescale.com>2011-09-01 13:57:21 +0800
commit7db399587fe4cd8d0e77491e9b2fad47c0a82be2 (patch)
tree7c4b34e73aff3607eb7dec6ea522203da355f5b3 /board/freescale/mx53_loco
parentea7a4199586b4b9cd9a4e13c0e420a4e1699a297 (diff)
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ENGR00155283: Set dpgdck0_2_en to 0 when freq is lower than 300MHz
1. Set dpgdck0_2_en to 0 when required freq is lower than 300Mhz. 2. When dpgdck0_2_en is 0, the formula to calculate output freq will be changed to 2 * freq * []. Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'board/freescale/mx53_loco')
-rw-r--r--board/freescale/mx53_loco/lowlevel_init.S9
1 files changed, 8 insertions, 1 deletions
diff --git a/board/freescale/mx53_loco/lowlevel_init.S b/board/freescale/mx53_loco/lowlevel_init.S
index ff879a6..dbcb074 100644
--- a/board/freescale/mx53_loco/lowlevel_init.S
+++ b/board/freescale/mx53_loco/lowlevel_init.S
@@ -56,8 +56,15 @@
.endm /* init_aips */
.macro setup_pll pll, freq
+ /*
+ * If freq < 300MHz, we need to set dpdck0_2_en to 0
+ */
+ ldr r0, =\freq
+ ldr r1, =0x300
+ cmp r0, r1
+ ldrcs r1, =0x00001232
+ ldrcc r1, =0x00000232
ldr r0, =\pll
- ldr r1, =0x00001232
str r1, [r0, #PLL_DP_CTL]
mov r1, #0x2
str r1, [r0, #PLL_DP_CONFIG]