ENGR00155891 : Fix reboot stress test failed issue

If we replace DCD mode with plug-in mode in u-boot , we found DDR not stable.
We should enable "Force Measurement" after the delay line
parameters is configured in the plug-in code, for example:
0x63fd9088 = 0x34333936
0x63fd9090 = 0x49434942
0x63fd90F8 = 0x00000800 "Force Measurement"
update all of mx53 DDR script, include mx53_smd,mx53_loco,mx53_evk,mx53_ard,
mx53_pcba, at the same time, mx53_pcba will change from DCD mode to plug-in
mode in flash_header.S

Signed-off-by: Robin Gong <B38343@freescale.com>

1 files changed, 41 insertions, 40 deletions

diff --git a/board/freescale/mx53_evk/flash_header.S b/board/freescale/mx53_evk/flash_header.S
index 6cadf3f..2fe3136 100644
--- a/board/freescale/mx53_evk/flash_header.S
+++ b/board/freescale/mx53_evk/flash_header.S
@@ -110,41 +110,42 @@ plugin_start:
 	REG_LD_AND_STR_OP(27, 0x0f8, 0x00000800)
 	REG_LD_AND_STR_OP(28, 0x07c, 0x01350138)
 	REG_LD_AND_STR_OP(29, 0x080, 0x01380139)
-	REG_LD_AND_STR_OP(30, 0x018, 0x00001710)
-	REG_LD_AND_STR_OP(31, 0x000, 0xc4110000)
-	REG_LD_AND_STR_OP(32, 0x00c, 0x4d5122d2)
-	REG_LD_AND_STR_OP(33, 0x010, 0x92d18a22)
-	REG_LD_AND_STR_OP(34, 0x014, 0x00c70092)
-	REG_LD_AND_STR_OP(35, 0x02c, 0x000026d2)
-	REG_LD_AND_STR_OP(36, 0x030, 0x009f000e)
-	REG_LD_AND_STR_OP(37, 0x008, 0x12272000)
-	REG_LD_AND_STR_OP(38, 0x004, 0x00030012)
-	REG_LD_AND_STR_OP(39, 0x01c, 0x04008010)
-	REG_LD_AND_STR_OP(40, 0x01c, 0x00008032)
-	REG_LD_AND_STR_OP(41, 0x01c, 0x00008033)
-	REG_LD_AND_STR_OP(42, 0x01c, 0x00008031)
-	REG_LD_AND_STR_OP(43, 0x01c, 0x0b5280b0)
-	REG_LD_AND_STR_OP(44, 0x01c, 0x04008010)
-	REG_LD_AND_STR_OP(45, 0x01c, 0x00008020)
+	REG_LD_AND_STR_OP(30, 0x0f8, 0x00000800)
+	REG_LD_AND_STR_OP(31, 0x018, 0x00001710)
+	REG_LD_AND_STR_OP(32, 0x000, 0xc4110000)
+	REG_LD_AND_STR_OP(33, 0x00c, 0x4d5122d2)
+	REG_LD_AND_STR_OP(34, 0x010, 0x92d18a22)
+	REG_LD_AND_STR_OP(35, 0x014, 0x00c70092)
+	REG_LD_AND_STR_OP(36, 0x02c, 0x000026d2)
+	REG_LD_AND_STR_OP(37, 0x030, 0x009f000e)
+	REG_LD_AND_STR_OP(38, 0x008, 0x12272000)
+	REG_LD_AND_STR_OP(39, 0x004, 0x00030012)
+	REG_LD_AND_STR_OP(40, 0x01c, 0x04008010)
+	REG_LD_AND_STR_OP(41, 0x01c, 0x00008032)
+	REG_LD_AND_STR_OP(42, 0x01c, 0x00008033)
+	REG_LD_AND_STR_OP(43, 0x01c, 0x00008031)
+	REG_LD_AND_STR_OP(44, 0x01c, 0x0b5280b0)
+	REG_LD_AND_STR_OP(45, 0x01c, 0x04008010)
 	REG_LD_AND_STR_OP(46, 0x01c, 0x00008020)
-	REG_LD_AND_STR_OP(47, 0x01c, 0x0a528030)
-	REG_LD_AND_STR_OP(48, 0x01c, 0x03c68031)
-	REG_LD_AND_STR_OP(49, 0x01c, 0x00448031)
-	REG_LD_AND_STR_OP(50, 0x01c, 0x04008018)
-	REG_LD_AND_STR_OP(51, 0x01c, 0x0000803a)
-	REG_LD_AND_STR_OP(52, 0x01c, 0x0000803b)
-	REG_LD_AND_STR_OP(53, 0x01c, 0x00008039)
-	REG_LD_AND_STR_OP(54, 0x01c, 0x0b528138)
-	REG_LD_AND_STR_OP(55, 0x01c, 0x04008018)
-	REG_LD_AND_STR_OP(56, 0x01c, 0x00008028)
+	REG_LD_AND_STR_OP(47, 0x01c, 0x00008020)
+	REG_LD_AND_STR_OP(48, 0x01c, 0x0a528030)
+	REG_LD_AND_STR_OP(49, 0x01c, 0x03c68031)
+	REG_LD_AND_STR_OP(50, 0x01c, 0x00448031)
+	REG_LD_AND_STR_OP(51, 0x01c, 0x04008018)
+	REG_LD_AND_STR_OP(52, 0x01c, 0x0000803a)
+	REG_LD_AND_STR_OP(53, 0x01c, 0x0000803b)
+	REG_LD_AND_STR_OP(54, 0x01c, 0x00008039)
+	REG_LD_AND_STR_OP(55, 0x01c, 0x0b528138)
+	REG_LD_AND_STR_OP(56, 0x01c, 0x04008018)
 	REG_LD_AND_STR_OP(57, 0x01c, 0x00008028)
-	REG_LD_AND_STR_OP(58, 0x01c, 0x0a528038)
-	REG_LD_AND_STR_OP(59, 0x01c, 0x03c68039)
-	REG_LD_AND_STR_OP(60, 0x01c, 0x00448039)
-	REG_LD_AND_STR_OP(61, 0x020, 0x00005800)
-	REG_LD_AND_STR_OP(62, 0x058, 0x00033335)
-	REG_LD_AND_STR_OP(63, 0x01c, 0x00000000)
-	REG_LD_AND_STR_OP(64, 0x040, 0x04b80003)
+	REG_LD_AND_STR_OP(58, 0x01c, 0x00008028)
+	REG_LD_AND_STR_OP(59, 0x01c, 0x0a528038)
+	REG_LD_AND_STR_OP(60, 0x01c, 0x03c68039)
+	REG_LD_AND_STR_OP(61, 0x01c, 0x00448039)
+	REG_LD_AND_STR_OP(62, 0x020, 0x00005800)
+	REG_LD_AND_STR_OP(63, 0x058, 0x00033335)
+	REG_LD_AND_STR_OP(64, 0x01c, 0x00000000)
+	REG_LD_AND_STR_OP(65, 0x040, 0x04b80003)
 	REG_LD_AND_STR_END(ESDCTL_BASE_ADDR)
 
 /*
@@ -221,13 +222,13 @@ return_sdp:
  */
 quit_plugin:
 	pop {r0-r6, lr}
-	ldr r4, DDR_DEST_ADDR
-	str r4, [r0]
-	ldr r4, COPY_SIZE
-	str r4, [r1]
-	mov r4, #0x400  /* Point to the second IVT table at offset 0x42C */
-	add r4, r4, #0x2C
-	str r4, [r2]
+	ldr r7, DDR_DEST_ADDR
+	str r7, [r0]
+	ldr r7, COPY_SIZE
+	str r7, [r1]
+	mov r7, #0x400  /* Point to the second IVT table at offset 0x42C */
+	add r7, r7, #0x2C
+	str r7, [r2]
 	mov r0, #1
 
 	bx lr  /* return back to ROM code */