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authorJason <r64343@freescale.com>2010-03-17 16:41:56 +0800
committerJason <r64343@freescale.com>2010-03-17 18:13:37 +0800
commit762d994929deb79569986bda8e4d7b56e06d14f0 (patch)
treef853eb6f029a9ab6683415863fbe85b4799d71cc /board/freescale/mx53_evk
parent029aff138902466bdfc1e62c761e89f8d37e83ea (diff)
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ENGR00121202 Add uboot support for MX53
Add uboot support for MX53 Signed-off-by:Jason Liu <r64343@freescale.com>
Diffstat (limited to 'board/freescale/mx53_evk')
-rw-r--r--board/freescale/mx53_evk/Makefile49
-rw-r--r--board/freescale/mx53_evk/config.mk3
-rw-r--r--board/freescale/mx53_evk/flash_header.S124
-rw-r--r--board/freescale/mx53_evk/lowlevel_init.S216
-rw-r--r--board/freescale/mx53_evk/mx53_evk.c449
-rw-r--r--board/freescale/mx53_evk/u-boot.lds73
6 files changed, 914 insertions, 0 deletions
diff --git a/board/freescale/mx53_evk/Makefile b/board/freescale/mx53_evk/Makefile
new file mode 100644
index 0000000..9e20903
--- /dev/null
+++ b/board/freescale/mx53_evk/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := mx53_evk.o
+SOBJS := lowlevel_init.o flash_header.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx53_evk/config.mk b/board/freescale/mx53_evk/config.mk
new file mode 100644
index 0000000..34f830a
--- /dev/null
+++ b/board/freescale/mx53_evk/config.mk
@@ -0,0 +1,3 @@
+LDSCRIPT := $(SRCTREE)/board/$(VENDOR)/$(BOARD)/u-boot.lds
+
+TEXT_BASE = 0x77800000
diff --git a/board/freescale/mx53_evk/flash_header.S b/board/freescale/mx53_evk/flash_header.S
new file mode 100644
index 0000000..4e88068
--- /dev/null
+++ b/board/freescale/mx53_evk/flash_header.S
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+
+#ifdef CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+
+#define CPU_2_BE_32(l) \
+ ((((l) & 0x000000FF) << 24) | \
+ (((l) & 0x0000FF00) << 8) | \
+ (((l) & 0x00FF0000) >> 8) | \
+ (((l) & 0xFF000000) >> 24))
+
+#define MXC_DCD_ITEM(i, addr, val) \
+dcd_node_##i: \
+ .word CPU_2_BE_32(addr) ; \
+ .word CPU_2_BE_32(val) ; \
+
+.section ".text.flasheader", "x"
+ b _start
+ .org CONFIG_FLASH_HEADER_OFFSET
+ivt_header: .word 0x402000D1 /* Tag=0xD1, Len=0x0020, Ver=0x40 */
+app_code_jump_v: .word _start
+reserv1: .word 0x0
+dcd_ptr: .word dcd_hdr
+boot_data_ptr: .word boot_data
+self_ptr: .word ivt_header
+app_code_csf: .word 0x0
+reserv2: .word 0x0
+
+boot_data: .word 0x77800000
+image_len: .word 256 * 1024
+plugin: .word 0x0
+
+dcd_hdr: .word 0x401002D2 /* Tag=0xD2, Len=65*8 + 4 + 4, Ver=0x40 */
+write_dcd_cmd: .word 0x040C02CC /* Tag=0xCC, Len=65*8 + 4, Param=4 */
+
+/* DCD */
+MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x554, 0x00380000)
+MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x558, 0x00380040)
+MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x72c, 0x00380000)
+MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x560, 0x00380000)
+MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x568, 0x00380040)
+MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x728, 0x00380000)
+MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x594, 0x00380000)
+MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x590, 0x00380040)
+MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x71c, 0x00380000)
+MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x584, 0x00380000)
+MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x57c, 0x00380040)
+MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x718, 0x00380000)
+MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x564, 0x00380040)
+MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x574, 0x00380000)
+MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x570, 0x00380000)
+MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x578, 0x00380000)
+MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x580, 0x00380040)
+MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x588, 0x00380000)
+MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x6f0, 0x00380000)
+MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x6f4, 0x00000200)
+MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x6fc, 0x00000000)
+MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x714, 0x00000000)
+MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x720, 0x00380000)
+MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x724, 0x06000000)
+MXC_DCD_ITEM(25, ESDCTL_BASE_ADDR + 0x88, 0x2b2f3031)
+MXC_DCD_ITEM(26, ESDCTL_BASE_ADDR + 0x90, 0x40363333)
+MXC_DCD_ITEM(27, ESDCTL_BASE_ADDR + 0xF8, 0x00000800)
+MXC_DCD_ITEM(28, ESDCTL_BASE_ADDR + 0x7c, 0x01310132)
+MXC_DCD_ITEM(29, ESDCTL_BASE_ADDR + 0x80, 0x0133014b)
+MXC_DCD_ITEM(30, ESDCTL_BASE_ADDR + 0x18, 0x000016d0)
+MXC_DCD_ITEM(31, ESDCTL_BASE_ADDR + 0x00, 0xc4110000)
+MXC_DCD_ITEM(32, ESDCTL_BASE_ADDR + 0x98, 0x00000f00)
+MXC_DCD_ITEM(33, ESDCTL_BASE_ADDR + 0x0C, 0x4d5122d2)
+MXC_DCD_ITEM(34, ESDCTL_BASE_ADDR + 0x10, 0x92d18a22)
+MXC_DCD_ITEM(35, ESDCTL_BASE_ADDR + 0x14, 0x00c70092)
+MXC_DCD_ITEM(36, ESDCTL_BASE_ADDR + 0x2c, 0x000026d2)
+MXC_DCD_ITEM(37, ESDCTL_BASE_ADDR + 0x30, 0x009f000e)
+MXC_DCD_ITEM(38, ESDCTL_BASE_ADDR + 0x08, 0x12272000)
+MXC_DCD_ITEM(39, ESDCTL_BASE_ADDR + 0x04, 0x00030012)
+MXC_DCD_ITEM(40, ESDCTL_BASE_ADDR + 0x1c, 0x04008010)
+MXC_DCD_ITEM(41, ESDCTL_BASE_ADDR + 0x1c, 0x00008032)
+MXC_DCD_ITEM(42, ESDCTL_BASE_ADDR + 0x1c, 0x00008033)
+MXC_DCD_ITEM(43, ESDCTL_BASE_ADDR + 0x1c, 0x00008031)
+MXC_DCD_ITEM(44, ESDCTL_BASE_ADDR + 0x1c, 0x0b5280b0)
+MXC_DCD_ITEM(45, ESDCTL_BASE_ADDR + 0x1c, 0x04008010)
+MXC_DCD_ITEM(46, ESDCTL_BASE_ADDR + 0x1c, 0x00008020)
+MXC_DCD_ITEM(47, ESDCTL_BASE_ADDR + 0x1c, 0x00008020)
+MXC_DCD_ITEM(48, ESDCTL_BASE_ADDR + 0x1c, 0x0a528030)
+MXC_DCD_ITEM(49, ESDCTL_BASE_ADDR + 0x1c, 0x03c68031)
+MXC_DCD_ITEM(50, ESDCTL_BASE_ADDR + 0x1c, 0x00468031)
+MXC_DCD_ITEM(51, ESDCTL_BASE_ADDR + 0x1c, 0x04008018)
+MXC_DCD_ITEM(52, ESDCTL_BASE_ADDR + 0x1c, 0x0000803a)
+MXC_DCD_ITEM(53, ESDCTL_BASE_ADDR + 0x1c, 0x0000803b)
+MXC_DCD_ITEM(54, ESDCTL_BASE_ADDR + 0x1c, 0x00008039)
+MXC_DCD_ITEM(55, ESDCTL_BASE_ADDR + 0x1c, 0x0b528138)
+MXC_DCD_ITEM(56, ESDCTL_BASE_ADDR + 0x1c, 0x04008018)
+MXC_DCD_ITEM(57, ESDCTL_BASE_ADDR + 0x1c, 0x00008028)
+MXC_DCD_ITEM(58, ESDCTL_BASE_ADDR + 0x1c, 0x00008028)
+MXC_DCD_ITEM(59, ESDCTL_BASE_ADDR + 0x1c, 0x0a528038)
+MXC_DCD_ITEM(60, ESDCTL_BASE_ADDR + 0x1c, 0x03c68039)
+MXC_DCD_ITEM(61, ESDCTL_BASE_ADDR + 0x1c, 0x00468039)
+MXC_DCD_ITEM(62, ESDCTL_BASE_ADDR + 0x20, 0x00005800)
+MXC_DCD_ITEM(63, ESDCTL_BASE_ADDR + 0x58, 0x00033337)
+MXC_DCD_ITEM(64, ESDCTL_BASE_ADDR + 0x1c, 0x00000000)
+MXC_DCD_ITEM(65, ESDCTL_BASE_ADDR + 0x18, 0x00001750)
+#endif
diff --git a/board/freescale/mx53_evk/lowlevel_init.S b/board/freescale/mx53_evk/lowlevel_init.S
new file mode 100644
index 0000000..c67c584
--- /dev/null
+++ b/board/freescale/mx53_evk/lowlevel_init.S
@@ -0,0 +1,216 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx53.h>
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+ /* explicitly disable L2 cache */
+ mrc 15, 0, r0, c1, c0, 1
+ bic r0, r0, #0x2
+ mcr 15, 0, r0, c1, c0, 1
+
+ /* reconfigure L2 cache aux control reg */
+ mov r0, #0xC0 /* tag RAM */
+ add r0, r0, #0x4 /* data RAM */
+ orr r0, r0, #(1 << 24) /* disable write allocate delay */
+ orr r0, r0, #(1 << 23) /* disable write allocate combine */
+ orr r0, r0, #(1 << 22) /* disable write allocate */
+
+ mcr 15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =0x77777777
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+.endm /* init_aips */
+
+.macro setup_pll pll, freq
+ ldr r2, =\pll
+ ldr r1, =0x00001232
+ str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ mov r1, #0x2
+ str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ str r3, [r2, #PLL_DP_OP]
+ str r3, [r2, #PLL_DP_HFS_OP]
+
+ str r4, [r2, #PLL_DP_MFD]
+ str r4, [r2, #PLL_DP_HFS_MFD]
+
+ str r5, [r2, #PLL_DP_MFN]
+ str r5, [r2, #PLL_DP_HFS_MFN]
+
+ ldr r1, =0x00001232
+ str r1, [r2, #PLL_DP_CTL]
+1: ldr r1, [r2, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 1b
+.endm
+
+.macro init_clock
+ ldr r0, CCM_BASE_ADDR_W
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+
+ mov r3, #DP_OP_800
+ mov r4, #DP_MFD_800
+ mov r5, #DP_MFN_800
+ setup_pll PLL1_BASE_ADDR, 800
+
+ mov r3, #DP_OP_400
+ mov r4, #DP_MFD_400
+ mov r5, #DP_MFN_400
+ setup_pll PLL3_BASE_ADDR, 400
+
+ /* Switch peripheral to PLL3 */
+ ldr r0, CCM_BASE_ADDR_W
+ ldr r1, CCM_VAL_0x00015154
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, CCM_VAL_0x02888945
+ orr r1, r1, #(1 << 16) /* Set DDR divider to run at 200MHz */
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure mux & divider change is effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ mov r3, #DP_OP_600
+ mov r4, #DP_MFD_600
+ mov r5, #DP_MFN_600
+ setup_pll PLL2_BASE_ADDR, 600
+
+ /* Switch peripheral to PLL2 */
+ ldr r0, CCM_BASE_ADDR_W
+ ldr r1, CCM_VAL_0x00809145 /* AHB is 120MHz, from PLL2 */
+ orr r1, r1, #(1 << 16) /* Set DDR divider to run at 300MHz */
+ orr r1, r1, #(2 << 19) /* Set AXI_B divider to run at 200MHz */
+ str r1, [r0, #CLKCTL_CBCDR]
+
+ ldr r1, CCM_VAL_0x00016154
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ /* make sure mux change is effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ mov r3, #DP_OP_216
+ mov r4, #DP_MFD_216
+ mov r5, #DP_MFN_216
+ setup_pll PLL3_BASE_ADDR, 216
+
+ /* Set the platform clock dividers */
+ ldr r0, PLATFORM_BASE_ADDR_W
+ ldr r1, PLATFORM_CLOCK_DIV_W
+ str r1, [r0, #PLATFORM_ICGC]
+
+ /* CPU 400M hz */
+ ldr r0, CCM_BASE_ADDR_W
+ mov r1, #1
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1. */
+ mov r1, #0x0
+ str r1, [r0, #CLKCTL_CCSR]
+
+ ldr r1, [r0, #CLKCTL_CSCDR1]
+ orr r1, r1, #0x3f
+ eor r1, r1, #0x3f
+ orr r1, r1, #0x21
+ str r1, [r0, #CLKCTL_CSCDR1]
+
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
+ str r1, [r0, #CLKCTL_CCGR7]
+
+ mov r1, #0x00000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ /* for cko - for ARM div by 8 */
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+#ifdef ENABLE_IMPRECISE_ABORT
+ mrs r1, spsr /* save old spsr */
+ mrs r0, cpsr /* read out the cpsr */
+ bic r0, r0, #0x100 /* clear the A bit */
+ msr spsr, r0 /* update spsr */
+ add lr, pc, #0x8 /* update lr */
+ movs pc, lr /* update cpsr */
+ nop
+ nop
+ nop
+ nop
+ msr spsr, r1 /* restore old spsr */
+#endif
+
+ /* ARM errata ID #468414 */
+ mrc 15, 0, r1, c1, c0, 1
+ orr r1, r1, #(1 << 5) /* enable L1NEON bit */
+ mcr 15, 0, r1, c1, c0, 1
+
+ init_l2cc
+
+ init_aips
+
+ init_clock
+
+ mov pc, lr
+
+/* Board level setting value */
+CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
+CCM_VAL_0x00016154: .word 0x00016154
+CCM_VAL_0x00809145: .word 0x00809145
+CCM_VAL_0x00015154: .word 0x00015154
+CCM_VAL_0x02888945: .word 0x02888945
+PLATFORM_BASE_ADDR_W: .word ARM_BASE_ADDR
+PLATFORM_CLOCK_DIV_W: .word 0x00000124
diff --git a/board/freescale/mx53_evk/mx53_evk.c b/board/freescale/mx53_evk/mx53_evk.c
new file mode 100644
index 0000000..1acfcc8
--- /dev/null
+++ b/board/freescale/mx53_evk/mx53_evk.c
@@ -0,0 +1,449 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx53.h>
+#include <asm/arch/mx53_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <imx_spi.h>
+
+#if CONFIG_I2C_MXC
+#include <i2c.h>
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+static enum boot_device boot_dev;
+u32 mx51_io_base_addr;
+
+static inline void setup_boot_device(void)
+{
+ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+ uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ;
+ uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3;
+
+ switch (bt_mem_ctl) {
+ case 0x4:
+ boot_dev = MMC_BOOT;
+ break;
+ case 0x8:
+ boot_dev = NAND_BOOT;
+ break;
+ case 0x3:
+ if (bt_mem_type)
+ boot_dev = SPI_NOR_BOOT;
+ break;
+ default:
+ boot_dev = UNKNOWN_BOOT;
+ break;
+ }
+}
+
+enum boot_device get_boot_device(void)
+{
+ return boot_dev;
+}
+
+u32 get_board_rev(void)
+{
+ return system_rev;
+}
+
+static inline void setup_soc_rev(void)
+{
+ system_rev = 0x53000 | CHIP_REV_1_0;
+}
+
+static inline void set_board_rev(int rev)
+{
+ system_rev |= (rev & 0xF) << 8;
+}
+
+inline int is_soc_rev(int rev)
+{
+ return (system_rev & 0xFF) - rev;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+static void setup_uart(void)
+{
+
+ /* UART1 RXD */
+ mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D11, 0x1E4);
+ mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
+
+ /* UART1 TXD */
+ mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D10, 0x1E4);
+}
+
+#ifdef CONFIG_I2C_MXC
+static void setup_i2c(unsigned int module_base)
+{
+ switch (module_base) {
+ case I2C1_BASE_ADDR:
+ /* i2c1 SDA */
+ mxc_request_iomux(MX53_PIN_CSI0_D8,
+ IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D8, PAD_CTL_SRE_FAST |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+ PAD_CTL_HYS_ENABLE);
+ /* i2c1 SCL */
+ mxc_request_iomux(MX53_PIN_CSI0_D9,
+ IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_CSI0_D9, PAD_CTL_SRE_FAST |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+ PAD_CTL_HYS_ENABLE);
+ break;
+ case I2C2_BASE_ADDR:
+ /* i2c2 SDA */
+ mxc_request_iomux(MX53_PIN_KEY_ROW3,
+ IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
+ PAD_CTL_SRE_FAST |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+ PAD_CTL_HYS_ENABLE);
+
+ /* i2c2 SCL */
+ mxc_request_iomux(MX53_PIN_KEY_COL3,
+ IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
+ INPUT_CTL_PATH0);
+ mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
+ PAD_CTL_SRE_FAST |
+ PAD_CTL_ODE_OPENDRAIN_ENABLE |
+ PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+ PAD_CTL_HYS_ENABLE);
+ break;
+ default:
+ printf("Invalid I2C base: 0x%x\n", module_base);
+ break;
+ }
+}
+
+void setup_core_voltages(void)
+{
+ unsigned char buf[4] = { 0 };
+
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+
+ /* Set core voltage VDDGP to 1.1V */
+ buf[0] = 0x45;
+ buf[1] = 0x4a;
+ buf[2] = 0x54;
+ if (i2c_write(0x8, 24, 1, buf, 3))
+ return;
+
+ /* Set DDR voltage VDDA to 1.225V */
+ buf[0] = 0;
+ buf[1] = 0x63;
+ buf[2] = 0x19;
+ if (i2c_write(0x8, 26, 1, buf, 3))
+ return;
+
+ /* Raise the core frequency to 800MHz */
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
+}
+#endif
+
+void spi_io_init(struct imx_spi_dev_t *dev)
+{
+ switch (dev->base) {
+ case CSPI1_BASE_ADDR:
+ /* Select mux mode: ALT4 mux port: MOSI of instance: ecspi1 */
+ mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0x104);
+ mxc_iomux_set_input(
+ MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, 0x3);
+
+ /* Select mux mode: ALT4 mux port: MISO of instance: ecspi1. */
+ mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0x104);
+ mxc_iomux_set_input(
+ MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT, 0x3);
+
+ if (dev->ss == 0) {
+ /* de-select SS1 of instance: ecspi1. */
+ mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x1E4);
+
+ /* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */
+ mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x104);
+ mxc_iomux_set_input(
+ MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, 0x3);
+ } else if (dev->ss == 1) {
+ /* de-select SS0 of instance: ecspi1. */
+ mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX53_PIN_EIM_EB2, 0x1E4);
+
+ /* mux mode: ALT0 mux port: SS1 of instance: ecspi1. */
+ mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0x104);
+ mxc_iomux_set_input(
+ MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, 0x2);
+ }
+
+ /* Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
+ mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0x104);
+ mxc_iomux_set_input(
+ MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, 0x3);
+
+ break;
+ case CSPI2_BASE_ADDR:
+ default:
+
+ break;
+ }
+}
+
+static void setup_fec(void)
+{
+ volatile unsigned int reg;
+
+ /*FEC_MDIO*/
+ mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, 0x1FC);
+ mxc_iomux_set_input(MUX_IN_FEC_FEC_MDI_SELECT_INPUT, 0x1);
+
+ /*FEC_MDC*/
+ mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_MDC, 0x004);
+
+ /* FEC RXD1 */
+ mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, 0x180);
+
+ /* FEC RXD0 */
+ mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, 0x180);
+
+ /* FEC TXD1 */
+ mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, 0x004);
+
+ /* FEC TXD0 */
+ mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, 0x004);
+
+ /* FEC TX_EN */
+ mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, 0x004);
+
+ /* FEC TX_CLK */
+ mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, 0x180);
+
+ /* FEC RX_ER */
+ mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, 0x180);
+
+ /* FEC CRS */
+ mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, 0x180);
+
+ /* phy reset: gpio7-6 */
+ mxc_request_iomux(MX53_PIN_ATA_DA_0, IOMUX_CONFIG_ALT1);
+
+ reg = readl(GPIO7_BASE_ADDR + 0x0);
+ reg &= ~0x40;
+ writel(reg, GPIO7_BASE_ADDR + 0x0);
+
+ reg = readl(GPIO7_BASE_ADDR + 0x4);
+ reg |= 0x40;
+ writel(reg, GPIO7_BASE_ADDR + 0x4);
+
+ udelay(500);
+
+ reg = readl(GPIO7_BASE_ADDR + 0x0);
+ reg |= 0x40;
+ writel(reg, GPIO7_BASE_ADDR + 0x0);
+
+}
+
+#ifdef CONFIG_CMD_MMC
+
+u32 *imx_esdhc_base_addr;
+
+int esdhc_gpio_init(void)
+{
+ u32 interface_esdhc = 0;
+ s32 status = 0;
+ uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+
+ interface_esdhc = (soc_sbmr & (0x00300000)) >> 20;
+
+ switch (interface_esdhc) {
+ case 0:
+ imx_esdhc_base_addr = (u32 *)MMC_SDHC1_BASE_ADDR;
+
+ mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
+
+ mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
+ mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
+ break;
+ case 2:
+ imx_esdhc_base_addr = (u32 *)MMC_SDHC3_BASE_ADDR;
+
+ mxc_request_iomux(MX53_PIN_ATA_RESET_B, IOMUX_CONFIG_ALT2);
+ mxc_request_iomux(MX53_PIN_ATA_IORDY, IOMUX_CONFIG_ALT2);
+ mxc_request_iomux(MX53_PIN_ATA_DATA8, IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA9, IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA10, IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA11, IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT4);
+ mxc_request_iomux(MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT4);
+
+ mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B, 0x1E4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_IORDY, 0xD4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA8, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA9, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA10, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA11, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA0, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA1, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA2, 0x1D4);
+ mxc_iomux_set_pad(MX53_PIN_ATA_DATA3, 0x1D4);
+
+ break;
+ default:
+ status = -1;
+ break;
+ }
+
+ return status;
+}
+
+int board_mmc_init(void)
+{
+ if (!esdhc_gpio_init())
+ return fsl_esdhc_mmc_init(gd->bd);
+ else
+ return -1;
+}
+
+#endif
+
+int board_init(void)
+{
+ setup_boot_device();
+ setup_soc_rev();
+
+ gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK; /* board id for linux */
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ setup_uart();
+ setup_fec();
+
+#ifdef CONFIG_I2C_MXC
+ setup_i2c(CONFIG_SYS_I2C_PORT);
+ setup_core_voltages();
+#endif
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ printf("Board: MX53 EVK ");
+
+ printf("1.0 [");
+
+
+ switch (__REG(SRC_BASE_ADDR + 0x8)) {
+ case 0x0001:
+ printf("POR");
+ break;
+ case 0x0009:
+ printf("RST");
+ break;
+ case 0x0010:
+ case 0x0011:
+ printf("WDOG");
+ break;
+ default:
+ printf("unknown");
+ }
+ printf("]\n");
+
+ printf("Boot Device: ");
+ switch (get_boot_device()) {
+ case NAND_BOOT:
+ printf("NAND\n");
+ break;
+ case SPI_NOR_BOOT:
+ printf("SPI NOR\n");
+ break;
+ case MMC_BOOT:
+ printf("MMC\n");
+ break;
+ case UNKNOWN_BOOT:
+ default:
+ printf("UNKNOWN\n");
+ break;
+ }
+ return 0;
+}
diff --git a/board/freescale/mx53_evk/u-boot.lds b/board/freescale/mx53_evk/u-boot.lds
new file mode 100644
index 0000000..fe5f4eb
--- /dev/null
+++ b/board/freescale/mx53_evk/u-boot.lds
@@ -0,0 +1,73 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+ board/freescale/mx53_evk/flash_header.o (.text.flasheader)
+ cpu/arm_cortexa8/start.o
+ board/freescale/mx53_evk/libmx53_evk.a (.text)
+ lib_arm/libarm.a (.text)
+ net/libnet.a (.text)
+ drivers/mtd/libmtd.a (.text)
+ drivers/mmc/libmmc.a (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o(.text)
+
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}