ENGR00137894-5 MX53 ARD:Support splashimage

This patch supports to use pwm wave to control
backlight. The pwm rate is 200Hz and the pwm
duty is 50%. Use 'lvds_num' env variable to
choose to use lvds0 or lvds1. Note that you
need to add 'splashimage' env variable to
set the memory address of the bmp image.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>

1 files changed, 207 insertions, 0 deletions

diff --git a/board/freescale/mx53_ard/mx53_ard.c b/board/freescale/mx53_ard/mx53_ard.c
index 8fddfda..01087be 100755
--- a/board/freescale/mx53_ard/mx53_ard.c
+++ b/board/freescale/mx53_ard/mx53_ard.c
@@ -28,6 +28,14 @@
 #include <asm/arch/mx53_pins.h>
 #include <asm/arch/iomux.h>
 #include <asm/errno.h>
+#if defined(CONFIG_VIDEO_MX5)
+#include <asm/imx_pwm.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+#include <linux/mxcfb.h>
+#include <ipu.h>
+#include <lcd.h>
+#endif
 #include <imx_spi.h>
 #include <netdev.h>
 
@@ -68,6 +76,45 @@ DECLARE_GLOBAL_DATA_PTR;
 static u32 system_rev;
 static enum boot_device boot_dev;
 
+#ifdef CONFIG_VIDEO_MX5
+extern unsigned char fsl_bmp_600x400[];
+extern int fsl_bmp_600x400_size;
+
+#if defined(CONFIG_BMP_8BPP)
+unsigned short colormap[256];
+#elif defined(CONFIG_BMP_16BPP)
+unsigned short colormap[65536];
+#else
+unsigned short colormap[16777216];
+#endif
+
+struct pwm_device pwm0 = {
+	.pwm_id = 0,
+	.pwmo_invert = 1,
+};
+
+struct pwm_device pwm1 = {
+	.pwm_id = 1,
+	.pwmo_invert = 1,
+};
+
+static int di = 1;
+#endif
+
+extern int ipuv3_fb_init(struct fb_videomode *mode, int di,
+			int interface_pix_fmt,
+			ipu_di_clk_parent_t di_clk_parent,
+			int di_clk_val);
+
+static struct fb_videomode lvds_xga = {
+	 "XGA", 60, 1024, 768, 15385, 220, 40, 21, 7, 60, 10,
+	 FB_SYNC_EXT,
+	 FB_VMODE_NONINTERLACED,
+	 0,
+};
+
+vidinfo_t panel_info;
+
 static inline void setup_boot_device(void)
 {
 	uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
@@ -628,6 +675,157 @@ int board_mmc_init(bd_t *bis)
 
 #endif
 
+#ifdef CONFIG_LCD
+void enable_pwm1_pad(void)
+{
+	mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT2);
+}
+
+void disable_pwm1_pad(void)
+{
+	unsigned int reg;
+
+	mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT1);
+	reg = readl(GPIO4_BASE_ADDR + 0x4);
+	reg |= 0x40000000;
+	writel(reg, GPIO4_BASE_ADDR + 0x4);
+	reg = readl(GPIO4_BASE_ADDR + 0x0);
+	reg |= 0x40000000;
+	writel(reg, GPIO4_BASE_ADDR + 0x0);
+}
+
+void enable_pwm1_clk(void)
+{
+	unsigned int reg;
+
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+	reg |= 0x30000;
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+}
+
+void disable_pwm1_clk(void)
+{
+	unsigned int reg;
+
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+	reg &= ~0x30000;
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+}
+
+void enable_pwm0_pad(void)
+{
+	mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT2);
+}
+
+void disable_pwm0_pad(void)
+{
+	unsigned int reg;
+
+	mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT1);
+	reg = readl(GPIO4_BASE_ADDR + 0x4);
+	reg |= 0x40000000;
+	writel(reg, GPIO4_BASE_ADDR + 0x4);
+	reg = readl(GPIO4_BASE_ADDR + 0x0);
+	reg |= 0x20000000;
+	writel(reg, GPIO4_BASE_ADDR + 0x0);
+}
+
+void enable_pwm0_clk(void)
+{
+	unsigned int reg;
+
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+	reg |= 0x3000;
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+}
+
+void disable_pwm0_clk(void)
+{
+	unsigned int reg;
+
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
+	reg &= ~0x3000;
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
+}
+
+void lcd_enable(void)
+{
+	char *s;
+	int ret;
+	unsigned int reg;
+
+	s = getenv("lvds_num");
+	di = simple_strtol(s, NULL, 10);
+
+	/* 200Hz PWM wave, 50% duty */
+	if (di == 1) {
+		pwm1.enable_pwm_pad = enable_pwm1_pad;
+		pwm1.disable_pwm_pad = disable_pwm1_pad;
+		pwm1.enable_pwm_clk = enable_pwm1_clk;
+		pwm1.disable_pwm_clk = disable_pwm1_clk;
+		imx_pwm_config(pwm1, 2500000, 5000000);
+		imx_pwm_enable(pwm1);
+	} else {
+		pwm0.enable_pwm_pad = enable_pwm0_pad;
+		pwm0.disable_pwm_pad = disable_pwm0_pad;
+		pwm0.enable_pwm_clk = enable_pwm0_clk;
+		pwm0.disable_pwm_clk = disable_pwm0_clk;
+		imx_pwm_config(pwm0, 2500000, 5000000);
+		imx_pwm_enable(pwm0);
+	}
+
+	ret = ipuv3_fb_init(&lvds_xga, di, IPU_PIX_FMT_RGB666,
+			DI_PCLK_LDB, 65000000);
+	if (ret)
+		puts("LCD cannot be configured\n");
+
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CSCMR2);
+	reg &= ~0xFC000000;
+	reg |= 0xB4000F00;
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CSCMR2);
+
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR6);
+	reg |= 0xF0000000;
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR6);
+
+	if (di == 1)
+		writel(0x40C, IOMUXC_BASE_ADDR + 0x8);
+	else
+		writel(0x201, IOMUXC_BASE_ADDR + 0x8);
+}
+#endif
+
+#ifdef CONFIG_VIDEO_MX5
+void panel_info_init(void)
+{
+	panel_info.vl_bpix = LCD_BPP;
+	panel_info.vl_col = lvds_xga.xres;
+	panel_info.vl_row = lvds_xga.yres;
+	panel_info.cmap = colormap;
+}
+#endif
+
+#ifdef CONFIG_SPLASH_SCREEN
+void setup_splash_image(void)
+{
+	char *s;
+	ulong addr;
+
+	s = getenv("splashimage");
+
+	if (s != NULL) {
+		addr = simple_strtoul(s, NULL, 16);
+
+#if defined(CONFIG_ARCH_MMU)
+		addr = ioremap_nocache(iomem_to_phys(addr),
+				fsl_bmp_600x400_size);
+#endif
+		memcpy((char *)addr, (char *)fsl_bmp_600x400,
+				fsl_bmp_600x400_size);
+	}
+}
+#endif
+
 #ifdef CONFIG_MXC_NAND
 void setup_nfc(void)
 {
@@ -756,6 +954,15 @@ int board_init(void)
 
 	weim_smc911x_iomux();
 	weim_cs1_settings();
+
+#ifdef CONFIG_VIDEO_MX5
+	panel_info_init();
+
+	gd->fb_base = CONFIG_FB_BASE;
+#ifdef CONFIG_ARCH_MMU
+	gd->fb_base = ioremap_nocache(iomem_to_phys(gd->fb_base), 0);
+#endif
+#endif
 	return 0;
 }