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| author | Anish Trivedi <anish@freescale.com> | 2011-06-20 14:34:03 -0500 |
|---|---|---|
| committer | Anish Trivedi <anish@freescale.com> | 2011-06-21 13:38:47 -0500 |
| commit | 65317a185c154cbe3f5dbbf3358cbd4ffbe52c81 (patch) | |
| tree | 08f31dfde39562c75b4d682e0a2b33cd6bc9a1e0 /board/freescale/mx51_bbg | |
| parent | de7bbfa11ec3f04d53e7b620a4f5371538b17253 (diff) | |
| download | u-boot-imx-65317a185c154cbe3f5dbbf3358cbd4ffbe52c81.zip u-boot-imx-65317a185c154cbe3f5dbbf3358cbd4ffbe52c81.tar.gz u-boot-imx-65317a185c154cbe3f5dbbf3358cbd4ffbe52c81.tar.bz2 | |
ENGR00151892 MX50: Workaround to prevent PLL1 from losing lock
PLL1 workaround to prevent it from losing lock:
(1) Disable AREN bit to avoid PLL1 restart during MFN change
(2) set PLL1 to ~864Mhz with MFI = 8, MFN = 180, MFD = 179, PDF = 0
(3) Manual restart PLL1
(4) Wait PLL1 lock
(5) Set PLL1 to 800Mhz with only change MFN to 60, others keep
(6) Set LDREQ bit to load new MFN
(7) Poll on LDREQ bit for MFN update to be completed
(8) Delay at least 4 us to avoid PLL1 instability window
(9) Switch ARM back to PLL1
Signed-off-by: Anish Trivedi <anish@freescale.com>
Diffstat (limited to 'board/freescale/mx51_bbg')
0 files changed, 0 insertions, 0 deletions