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authorTerry Lv <r65388@freescale.com>2009-12-11 15:19:57 +0800
committerTerry Lv <r65388@freescale.com>2009-12-11 15:19:57 +0800
commit53f07baf9167201943561651ba9f3587f1b8edc9 (patch)
treed690a1e5f115cec6bffa1b6e8f051ca3aa083ea0 /board/freescale/mx51_bbg
parent1ee27e13d6fdb19d297f8d1d6d3d7d8449d0361e (diff)
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ENGR00119224: mmu support for mx51 3stack and mx51 bbg
mmu support for mx51 3stack and mx51 bbg. Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'board/freescale/mx51_bbg')
-rw-r--r--board/freescale/mx51_bbg/flash_header.S3
-rw-r--r--board/freescale/mx51_bbg/mx51_bbg.c62
2 files changed, 63 insertions, 2 deletions
diff --git a/board/freescale/mx51_bbg/flash_header.S b/board/freescale/mx51_bbg/flash_header.S
index 6790679..17a5c59 100644
--- a/board/freescale/mx51_bbg/flash_header.S
+++ b/board/freescale/mx51_bbg/flash_header.S
@@ -108,6 +108,5 @@ MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
dcd_data_end:
-image_len: .word 0x100000
-//image_len: .word _end - _start
+image_len: .word __u_boot_cmd_end - TEXT_BASE
#endif
diff --git a/board/freescale/mx51_bbg/mx51_bbg.c b/board/freescale/mx51_bbg/mx51_bbg.c
index 8a45a78..4279ac6 100644
--- a/board/freescale/mx51_bbg/mx51_bbg.c
+++ b/board/freescale/mx51_bbg/mx51_bbg.c
@@ -41,6 +41,11 @@
#include <fsl_esdhc.h>
#endif
+#ifdef CONFIG_ARCH_MMU
+#include <asm/mmu.h>
+#include <asm/arch/mmu.h>
+#endif
+
#ifdef CONFIG_FSL_ANDROID
#include <mxc_keyb.h>
#include <part.h>
@@ -140,6 +145,63 @@ inline int is_soc_rev(int rev)
return (system_rev & 0xFF) - rev;
}
+#ifdef CONFIG_ARCH_MMU
+void board_mmu_init(void)
+{
+ unsigned long ttb_base = PHYS_SDRAM_1 + 0x4000;
+ unsigned long i;
+
+ /*
+ * Set the TTB register
+ */
+ asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+ /*
+ * Set the Domain Access Control Register
+ */
+ i = ARM_ACCESS_DACR_DEFAULT;
+ asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+ /*
+ * First clear all TT entries - ie Set them to Faulting
+ */
+ memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+ /* Actual Virtual Size Attributes Function */
+ /* Base Base MB cached? buffered? access permissions */
+ /* xxx00000 xxx00000 */
+ X_ARM_MMU_SECTION(0x000, 0x200, 0x1,
+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+ ARM_ACCESS_PERM_RW_RW); /* ROM */
+ X_ARM_MMU_SECTION(0x1FF, 0x1FF, 0x001,
+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+ ARM_ACCESS_PERM_RW_RW); /* IRAM */
+ X_ARM_MMU_SECTION(0x300, 0x300, 0x100,
+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+ ARM_ACCESS_PERM_RW_RW); /* GPU */
+ X_ARM_MMU_SECTION(0x400, 0x400, 0x200,
+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+ ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
+ X_ARM_MMU_SECTION(0x600, 0x600, 0x300,
+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+ ARM_ACCESS_PERM_RW_RW); /* periperals */
+ X_ARM_MMU_SECTION(0x900, 0x000, 0x1FF,
+ ARM_CACHEABLE, ARM_BUFFERABLE,
+ ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x900, 0x900, 0x200,
+ ARM_CACHEABLE, ARM_BUFFERABLE,
+ ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x900, 0xE00, 0x200,
+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+ ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+ X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10,
+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+ ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
+ X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040,
+ ARM_UNCACHEABLE, ARM_UNBUFFERABLE,
+ ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
+}
+#endif
+
int dram_init(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;