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| author | Terry Lv <r65388@freescale.com> | 2010-02-24 18:34:13 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2010-03-04 14:55:00 +0800 |
| commit | bd6578e46d1ba93ffe6e00147704d7d18c7e5573 (patch) | |
| tree | 424b9a30a2e791ff267b2aaa27d0d52186693b8e /board/freescale/mx51_3stack | |
| parent | 871825c1148b233fb562c09204700b59fcd28b67 (diff) | |
| download | u-boot-imx-bd6578e46d1ba93ffe6e00147704d7d18c7e5573.zip u-boot-imx-bd6578e46d1ba93ffe6e00147704d7d18c7e5573.tar.gz u-boot-imx-bd6578e46d1ba93ffe6e00147704d7d18c7e5573.tar.bz2 | |
ENGR00120520: Enable MMU for mx51 and mx35
MMU enable code is missed in mx51 and mx35 u-boot.
So add these codes.
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'board/freescale/mx51_3stack')
| -rw-r--r-- | board/freescale/mx51_3stack/mx51_3stack.c | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/board/freescale/mx51_3stack/mx51_3stack.c b/board/freescale/mx51_3stack/mx51_3stack.c index af5d3df..7ec3b1d 100644 --- a/board/freescale/mx51_3stack/mx51_3stack.c +++ b/board/freescale/mx51_3stack/mx51_3stack.c @@ -112,7 +112,12 @@ u32 get_board_rev(void) static inline void setup_soc_rev(void) { int reg; - reg = __REG(ROM_SI_REV); +#ifdef CONFIG_ARCH_MMU + reg = __REG(0x20000000 + ROM_SI_REV); /* Virtual address */ +#else + reg = __REG(ROM_SI_REV); /* Virtual address */ +#endif + switch (reg) { case 0x02: system_rev = 0x51000 | CHIP_REV_1_1; @@ -144,13 +149,13 @@ void board_mmu_init(void) /* * Set the TTB register */ - asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/); + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/); /* * Set the Domain Access Control Register */ i = ARM_ACCESS_DACR_DEFAULT; - asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/); + asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/); /* * First clear all TT entries - ie Set them to Faulting @@ -192,6 +197,15 @@ void board_mmu_init(void) X_ARM_MMU_SECTION(0xCC0, 0xCC0, 0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */ + + /* Workaround for arm errata #709718 */ + /* Setup PRRR so device is always mapped to non-shared */ + asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(i) : /*:*/); + i &= (~(3 << 0x10)); + asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(i) /*:*/); + + /* Enable MMU */ + MMU_ON(); } #endif |