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author | Anson Huang <b20788@freescale.com> | 2011-05-16 11:51:31 +0800 |
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committer | Robby Cai <R63905@freescale.com> | 2011-07-22 13:15:57 +0800 |
commit | 90479372456d62d426bc3b3241de1412c68f24a5 (patch) | |
tree | 2fe434af26a06d110a42dfa566156e0ad5a74fd8 /board/freescale/mx50_rdp | |
parent | 6667da86ca1582222416defdcbf8e6d41bc03d28 (diff) | |
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ENGR00143438 [MX50 RD3]DCDC_3V15 GPIO change
Change DCDC_3V15's GPIO setting for REV-D.
Signed-off-by: Anson Huang <b20788@freescale.com>
(cherry picked from commit 28a8e166c6a8fa001325f88ef06e5a81f6ed82a9)
Diffstat (limited to 'board/freescale/mx50_rdp')
-rw-r--r-- | board/freescale/mx50_rdp/mx50_rdp.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/mx50_rdp/mx50_rdp.c b/board/freescale/mx50_rdp/mx50_rdp.c index 7687def..a56284f 100644 --- a/board/freescale/mx50_rdp/mx50_rdp.c +++ b/board/freescale/mx50_rdp/mx50_rdp.c @@ -655,10 +655,10 @@ static void setup_fec(void) reg |= (1 << 15); writel(reg, GPIO4_BASE_ADDR + 0x4); - /* DCDC_PWREN(GP4_16) set to 0 to enable DCDC_3V15 */ + /* DCDC_PWREN(GP4_16) set to 1 to enable DCDC_3V15 */ mxc_request_iomux(MX50_PIN_ECSPI2_SCLK, IOMUX_CONFIG_ALT1); reg = readl(GPIO4_BASE_ADDR + 0x0); - reg &= ~(1 << 16); + reg |= (1 << 16); writel(reg, GPIO4_BASE_ADDR + 0x0); reg = readl(GPIO4_BASE_ADDR + 0x4); |