ENGR00133744: Merge mx50_arm2 to mx50_rdp

Merge mx50_arm2 to mx50_rdp.

Signed-off-by: Terry Lv <r65388@freescale.com>

2 files changed, 1365 insertions, 31 deletions

diff --git a/board/freescale/mx50_rdp/flash_header.S b/board/freescale/mx50_rdp/flash_header.S
index 7a547d9..98eb3eb 100644
--- a/board/freescale/mx50_rdp/flash_header.S
+++ b/board/freescale/mx50_rdp/flash_header.S
@@ -213,6 +213,7 @@ plugin2:           .long 0x0
  *===========================================================================*/
 
 plugin_start:
+
 /* Save the return address and the function arguments */
 	push    {r0-r6, r8, lr}
 
@@ -289,6 +290,8 @@ wait_pll1_lock:
 	str r1, [r0, #0x80]
 	str r1, [r0, #0x84]
 
+#if defined(CONFIG_LPDDR2)
+
 /* DDR clock setting -- Set DDR to be div 3 to get 266MHz */
 /* setmem /32 0x53FD4098 = 0x80000003 */
 	ldr r1, =0x80000003
@@ -303,63 +306,64 @@ wait_pll1_lock:
 /*=============================================================================
  * IOMUX
  *===========================================================================*/
-    ldr r0, =0x53fa8600
-    mov r1, #0x04000000
-    ldr r3, =0x00180000
-    mov r2, #0x0
+	ldr r0, =0x53fa8600
+	mov r1, #0x04000000
+	ldr r3, =0x00180000
+	mov r2, #0x0
 //setmem /32 0x53fa86ac = 0x04000000
 //IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, ddr_sel=2'b01 (LPDDR2)
-    str r1, [r0, #0xac]
+	str r1, [r0, #0xac]
 //setmem /32 0x53fa86a4 = 0x00180000
 //IOMUXC_SW_PAD_CTL_GRP_CTLDS, dse=3'b100
-    str r3, [r0, #0xa4]
+	str r3, [r0, #0xa4]
 //setmem /32 0x53fa8668 = 0x00180000
 //IOMUXC_SW_PAD_CTL_GRP_ADDDS, dse=3'b100
-    str r3, [r0, #0x68]
+	str r3, [r0, #0x68]
 //setmem /32 0x53fa8698 = 0x00180000
 //IOMUXC_SW_PAD_CTL_GRP_B0DS, dse=3'b100
-    str r3, [r0, #0x98]
+	str r3, [r0, #0x98]
 //setmem /32 0x53fa86a0 = 0x00180000
 //IOMUXC_SW_PAD_CTL_GRP_B1DS, dse=3'b100
-    str r3, [r0, #0xa0]
+	str r3, [r0, #0xa0]
 //setmem /32 0x53fa86a8 = 0x00180000
 //IOMUXC_SW_PAD_CTL_GRP_B2DS, dse=3'b100
-    str r3, [r0, #0xa8]
+	str r3, [r0, #0xa8]
 //setmem /32 0x53fa86b4 = 0x00180000
 //IOMUXC_SW_PAD_CTL_GRP_B3DS, dse=3'b100
-    str r3, [r0, #0xb4]
+	str r3, [r0, #0xb4]
 
-    ldr r0, =0x53fa8400
+	ldr r0, =0x53fa8400
 //setmem /32 0x53fa8498 = 0x00180000
 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
-    str r3, [r0, #0x98]
+	str r3, [r0, #0x98]
 //setmem /32 0x53fa849c = 0x00180000
 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
-    str r3, [r0, #0x9c]
+	str r3, [r0, #0x9c]
 //setmem /32 0x53fa84f0 = 0x00180000
 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, dse=3'b100
-    str r3, [r0, #0xf0]
+	str r3, [r0, #0xf0]
 //setmem /32 0x53fa8500 = 0x00180000
 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, dse=3'b100
-    str r3, [r0, #0x100]
+	str r3, [r0, #0x100]
 //setmem /32 0x53fa84c8 = 0x00180000
 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, dse=3'b100
-    str r3, [r0, #0xc8]
+	str r3, [r0, #0xc8]
 //setmem /32 0x53fa8528 = 0x00180000
 //IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, dse=3'b100
-    str r3, [r0, #0x128]
+	str r3, [r0, #0x128]
 //setmem /32 0x53fa84f4 = 0x00180000
 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, dse=3'b100
-    str r3, [r0, #0xf4]
+	str r3, [r0, #0xf4]
 //setmem /32 0x53fa84fc = 0x00180000
 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, dse=3'b100
-    str r3, [r0, #0xfc]
+	str r3, [r0, #0xfc]
 //setmem /32 0x53fa84cc = 0x00180000
 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, dse=3'b100
-    str r3, [r0, #0xcc]
+	str r3, [r0, #0xcc]
 //setmem /32 0x53fa8524 = 0x00180000
 //IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, dse=3'b100
-    str r3, [r0, #0x124]
+	str r3, [r0, #0x124]
+
 
 //*===========================================
 //   DDR controller setting
@@ -395,6 +399,12 @@ wait_pll1_lock:
 	str r1, [r0, #0x124]
 #endif
 
+#if defined(CONFIG_MX50_RDP)
+
+/*===========================================================================
+ * DDR setting
+ *===========================================================================*/
+
 //setmem /32 0x14000000 = 0x00000500
     ldr r1, =0x00000500
     str r1, [r0, #0x0]
@@ -701,19 +711,1044 @@ wait_pll1_lock:
     ldr r1, =0x000a0b01
     str r1, [r0, #0x25c]
 
+#elif defined(CONFIG_MX50_ARM2)
 
-//*===================================
-// Start ddr init sequence
-//*===================================
-//setmem /32 0x14000000 = 0x00000501  // bit[0]: start
-    ldr r1, =0x00000501
-    str r1, [r0, #0x0]
+/*=============================================================================
+ * DDR setting
+ *===========================================================================*/
+
+/* setmem /32 0x14000000	= 0x00000500 */
+	ldr r1, =0x00000500
+	str r1, [r0, #0x0]
+/* setmem /32 0x14000004	= 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4]
+/* setmem /32 0x14000008	= 0x0000001b */
+	ldr r1, =0x0000001b
+	str r1, [r0, #0x8]
+/* setmem /32 0x1400000c	= 0x0000d056 */
+	ldr r1, =0x0000d056
+	str r1, [r0, #0xc]
+/* setmem /32 0x14000010	= 0x0000010b */
+	ldr r1, =0x0000010b
+	str r1, [r0, #0x10]
+/* setmem /32 0x14000014	= 0x00000a6b */
+	ldr r1, =0x00000a6b
+	str r1, [r0, #0x14]
+/* setmem /32 0x14000018	= 0x02020d0c */
+        ldr r1, =0x02020d0c
+        str r1, [r0, #0x18]
+/* setmem /32 0x1400001c	= 0x0c110302 */
+	ldr r1, =0x0c110302
+	str r1, [r0, #0x1c]
+/* setmem /32 0x14000020	= 0x05020503 */
+	ldr r1, =0x05020503
+	str r1, [r0, #0x20]
+/* setmem /32 0x14000024	= 0x00000105 */
+	ldr r1, =0x00000105
+	str r1, [r0, #0x24]
+/* setmem /32 0x14000028	= 0x01000403 */
+	ldr r1, =0x01000403
+	str r1, [r0, #0x28]
+/* setmem /32 0x1400002c	= 0x09040501 */
+	ldr r1, =0x09040501
+	str r1, [r0, #0x2c]
+/* setmem /32 0x14000030	= 0x02000000 */
+	ldr r1, =0x02000000
+	str r1, [r0, #0x30]
+/* setmem /32 0x14000034	= 0x00000e02 */
+	ldr r1, =0x00000e02
+	str r1, [r0, #0x34]
+/* setmem /32 0x14000038	= 0x00000006 */
+	ldr r1, =0x00000006
+	str r1, [r0, #0x38]
+/* setmem /32 0x1400003c	= 0x00002301 */
+	ldr r1, =0x00002301
+	str r1, [r0, #0x3c]
+/* setmem /32 0x14000040	= 0x00050300 */
+	ldr r1, =0x00050300
+	str r1, [r0, #0x40]
+/* setmem /32 0x14000044	= 0x00000300 */
+	ldr r1, =0x00000300
+	str r1, [r0, #0x44]
+/* setmem /32 0x14000048	= 0x00260026 */
+	ldr r1, =0x00260026
+	str r1, [r0, #0x48]
+/* setmem /32 0x1400004c	= 0x00010000 */
+	ldr r1, =0x00010000
+	str r1, [r0, #0x4c]
+/* setmem /32 0x1400005c	= 0x02000000 */
+	ldr r1, =0x02000000
+	str r1, [r0, #0x5c]
+/* setmem /32 0x14000060	= 0x00000002 */
+	ldr r1, =0x00000002
+	str r1, [r0, #0x60]
+/* setmem /32 0x14000064	= 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x64]
+/* setmem /32 0x14000068	= 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x68]
+/* setmem /32 0x1400006c	= 0x00040042 */
+	ldr r1, =0x00040042
+	str r1, [r0, #0x6c]
+/* setmem /32 0x14000070	= 0x00000001 */
+	ldr r1, =0x00000001
+	str r1, [r0, #0x70]
+/* setmem /32 0x14000074	= 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x74]
+/* setmem /32 0x14000078	= 0x00040042 */
+	ldr r1, =0x00040042
+	str r1, [r0, #0x78]
+/* setmem /32 0x1400007c	= 0x00000001 */
+	ldr r1, =0x00000001
+	str r1, [r0, #0x7c]
+/* setmem /32 0x14000080	= 0x010b0000 */
+	ldr r1, =0x010b0000
+	str r1, [r0, #0x80]
+/* setmem /32 0x14000084	= 0x00000060 */
+	ldr r1, =0x00000060
+	str r1, [r0, #0x84]
+/* setmem /32 0x14000088	= 0x02400018 */
+        ldr r1, =0x02400018
+        str r1, [r0, #0x88]
+/* setmem /32 0x1400008c	= 0x01000e00 */
+        ldr r1, =0x01000e00
+        str r1, [r0, #0x8c]
+/* setmem /32 0x14000090	= 0x0a010101 */
+        ldr r1, =0x0a010101
+        str r1, [r0, #0x90]
+/* setmem /32 0x14000094	= 0x01011f1f */
+        ldr r1, =0x01011f1f
+        str r1, [r0, #0x94]
+/* setmem /32 0x14000098	= 0x01010101 */
+        ldr r1, =0x01010101
+        str r1, [r0, #0x98]
+/* setmem /32 0x1400009c	= 0x00030101 */
+        ldr r1, =0x00030101
+        str r1, [r0, #0x9c]
+/* setmem /32 0x140000a0	= 0x00010000 */
+        ldr r1, =0x00010000
+        str r1, [r0, #0xa0]
+/* setmem /32 0x140000a4	= 0x00010000 */
+        ldr r1, =0x00010000
+        str r1, [r0, #0xa4]
+/* setmem /32 0x140000a8	= 0x00000000 */
+        ldr r1, =0x00000000
+        str r1, [r0, #0xa8]
+/* setmem /32 0x140000ac	= 0x0000ffff */
+        ldr r1, =0x0000ffff
+        str r1, [r0, #0xac]
+/* setmem /32 0x140000c8	= 0x02020101 */
+        ldr r1, =0x02020101
+        str r1, [r0, #0xc8]
+/* setmem /32 0x140000cc	= 0x01000000 */
+        ldr r1, =0x01000000
+        str r1, [r0, #0xcc]
+/* setmem /32 0x140000d0	= 0x06060606 */
+        ldr r1, =0x06060606
+        str r1, [r0, #0xd0]
+/* setmem /32 0x140000d4	= 0x06060606 */
+        ldr r1, =0x06060606
+        str r1, [r0, #0xd4]
+/* setmem /32 0x140000d8	= 0x00000102 */
+        ldr r1, =0x00000102
+        str r1, [r0, #0xd8]
+/* setmem /32 0x140000dc	= 0x0000ffff */
+        ldr r1, =0x0000ffff
+        str r1, [r0, #0xdc]
+/* setmem /32 0x140000e0	= 0x0000ffff */
+        ldr r1, =0x0000ffff
+        str r1, [r0, #0xdc]
+/* setmem /32 0x140000e4	= 0x02020000 */
+        ldr r1, =0x02020000
+        str r1, [r0, #0xe4]
+/* setmem /32 0x140000e8	= 0x02020202 */
+        ldr r1, =0x02020202
+        str r1, [r0, #0xe8]
+/* setmem /32 0x140000ec	= 0x00000202 */
+        ldr r1, =0x00000202
+        str r1, [r0, #0xec]
+/* setmem /32 0x140000f0	= 0x01010064 */
+        ldr r1, =0x01010064
+        str r1, [r0, #0xf0]
+/* setmem /32 0x140000f4	= 0x01010101 */
+        ldr r1, =0x01010101
+        str r1, [r0, #0xf4]
+/* setmem /32 0x140000f8	= 0x00010101 */
+        ldr r1, =0x00010101
+        str r1, [r0, #0xf8]
+/* setmem /32 0x140000fc	= 0x00000064 */
+        ldr r1, =0x00000064
+        str r1, [r0, #0xfc]
+/* setmem /32 0x14000100	= 0x00000000 */
+        ldr r1, =0x00000000
+        str r1, [r0, #0x100]
+/* setmem /32 0x14000104	= 0x02000802 */
+        ldr r1, =0x02000802
+        str r1, [r0, #0x104]
+/* setmem /32 0x14000108	= 0x04080000 */
+        ldr r1, =0x04080000
+        str r1, [r0, #0x108]
+/* setmem /32 0x1400010c	= 0x04080408 */
+        ldr r1, =0x04080408
+        str r1, [r0, #0x10c]
+/* setmem /32 0x14000110	= 0x04080408 */
+        ldr r1, =0x04080408
+        str r1, [r0, #0x110]
+/* setmem /32 0x14000114	= 0x03060408 */
+        ldr r1, =0x03060408
+        str r1, [r0, #0x114]
+/* setmem /32 0x14000118	= 0x01010002 */
+        ldr r1, =0x01010002
+        str r1, [r0, #0x118]
+/* setmem /32 0x1400011c	= 0x00001000 */
+        ldr r1, =0x00001000
+        str r1, [r0, #0x11c]
+/* setmem /32 0x14000200	= 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x200]
+/* setmem /32 0x14000204	= 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x204]
+/* setmem /32 0x14000208	= 0xf5003a27 */
+	ldr r1, =0xf5003a27
+	str r1, [r0, #0x208]
+/* setmem /32 0x14000210	= 0xf5003a27 */
+	str r1, [r0, #0x210]
+/* setmem /32 0x14000218	= 0xf5003a27 */
+	str r1, [r0, #0x218]
+/* setmem /32 0x14000220	= 0xf5003a27 */
+	str r1, [r0, #0x220]
+/* setmem /32 0x14000228	= 0xf5003a27 */
+	str r1, [r0, #0x228]
+/* setmem /32 0x1400020c        = 0x074002e1 */
+        ldr r1, =0x074002e1
+        str r1, [r0, #0x20c]
+/* setmem /32 0x14000214        = 0x074002e1 */
+        str r1, [r0, #0x214]
+/* setmem /32 0x1400021c        = 0x074002e1 */
+        str r1, [r0, #0x21c]
+/* setmem /32 0x14000224        = 0x074002e1 */
+        str r1, [r0, #0x224]
+/* setmem /32 0x1400022c	= 0x074002e1 */
+	str r1, [r0, #0x22c]
+/* setmem /32 0x14000230	= 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x230]
+/* setmem /32 0x14000234	= 0x00810006 */
+	ldr r1, =0x00810006
+	str r1, [r0, #0x234]
+/* setmem /32 0x14000238	= 0x20099414 */
+	ldr r1, =0x20099414
+	str r1, [r0, #0x238]
+/* setmem /32 0x14000240	= 0x20099414 */
+	str r1, [r0, #0x240]
+/* setmem /32 0x14000248	= 0x20099414 */
+	str r1, [r0, #0x248]
+/* setmem /32 0x14000250	= 0x20099414 */
+	str r1, [r0, #0x250]
+/* setmem /32 0x14000258	= 0x20099414 */
+	str r1, [r0, #0x258]
+/* setmem /32 0x1400023c	= 0x000a0b01 */
+	ldr r1, =0x000a0b01
+	str r1, [r0, #0x23c]
+/* setmem /32 0x14000244	= 0x000a0b01 */
+	str r1, [r0, #0x244]
+/* setmem /32 0x1400024c	= 0x000a0b01 */
+	str r1, [r0, #0x24c]
+/* setmem /32 0x14000254	= 0x000a0b01 */
+	str r1, [r0, #0x254]
+/* setmem /32 0x1400025c	= 0x000a0b01 */
+	str r1, [r0, #0x25c]
+#else
+#	error "Unsupported board!"
+#endif
+
+/* Start ddr */
+/* setmem /32 0x14000000 = 0x00000501  // bit[0]: start */
+	ldr r1, =0x00000501
+	str r1, [r0, #0x0]
+/* poll to make sure it is done */
+1:
+	ldr r1, [r0, #0xa8]
+	ands r1, r1, #0x10
+	beq 1b
+
+#elif defined(CONFIG_DDR2)
+
+/*  DDR clock setting -- Set DDR to be div 3 to get 266MHz     */
+	ldr	r0, =CCM_BASE_ADDR
+	ldr     r1, =0xA0000043
+	str     r1, [r0, #0x94]
+
+/*	DDR clock from PLL1 */
+	ldr     r1, =0x00000803
+	str     r1, [r0, #0x90]
+
+/*	---------- IOMUX SETUP ---------- */
+/*	0x53fa86ac = 0x02000000  IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, ddr_sel=2'b01*/
+	ldr r0, =0x53fa8600
+	mov r1, #0x02000000
+	mov r3, #0x00200000
+	mov r2, #0x0
+	str r1, [r0, #0xac]
+/*	These DSE values seem to make thing work */
+/*	0x53fa86a4 = 0x00200000  IOMUXC_SW_PAD_CTL_GRP_CTLDS, dse=3'b100*/
+	str r3, [r0, #0xa4]
+/*	0x53fa8668 = 0x00200000  IOMUXC_SW_PAD_CTL_GRP_ADDDS, dse=3'b100*/
+	str r3, [r0, #0x68]
+/*	0x53fa8698 = 0x00200000  IOMUXC_SW_PAD_CTL_GRP_B0DS, dse=3'b100*/
+	str r3, [r0, #0x98]
+/*	0x53fa86a0 = 0x00200000  IOMUXC_SW_PAD_CTL_GRP_B1DS, dse=3'b100*/
+	str r3, [r0, #0xa0]
+/*	0x53fa86a8 = 0x00200000  IOMUXC_SW_PAD_CTL_GRP_B2DS, dse=3'b100*/
+	str r3, [r0, #0xa8]
+/*	0x53fa86b4 = 0x00200000  IOMUXC_SW_PAD_CTL_GRP_B3DS, dse=3'b100*/
+	str r3, [r0, #0xb4]
+/*	0x53fa8498 = 0x00200000  IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
+	ldr r0, =0x53fa8400
+	str r3, [r0, #0x98]
+/*	0x53fa849c = 0x00200000  IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
+	str r3, [r0, #0x9c]
+/*	0x53fa84f0 = 0x00200000  IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, dse=3'b100*/
+	str r3, [r0, #0xf0]
+/*	0x53fa8500 = 0x00200000  IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, dse=3'b100*/
+	ldr r0, =0x53fa8500
+	str r3, [r0, #0x00]
+/*	0x53fa84c8 = 0x00200000  IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, dse=3'b100*/
+	ldr r0, =0x53fa8400
+	str r3, [r0, #0xc8]
+/*	0x53fa8528 = 0x00200000  IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, dse=3'b100*/
+	ldr r0, =0x53fa8500
+	str r3, [r0, #0x28]
+
+/*	0x53fa84f4 = 0x00200080
+	IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, dse=3'b100 , pke=1, pue=1
+	*/
+	ldr r0, =0x53fa8400
+	orr r3, r3,#0x00000080
+	str r3, [r0, #0xf4]
+
+/*	0x53fa84fc = 0x00200080
+	IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, dse=3'b100 , pke=1, pue=1
+	*/
+	str r3, [r0, #0xfc]
+
+/*	0x53fa84cc = 0x00200080
+	IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, dse=3'b100 , pke=1, pue=1
+	*/
+	str r3, [r0, #0xcc]
+	ldr r0, =0x53fa8500
+
+/*	0x53fa8524 = 0x00200080
+	IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, dse=3'b100 , pke=1, pue=1
+	*/
+	str r3, [r0, #0x24]
+
+/*	---------- DDR SETUP ---------- */
+//*===========================================
+//   DDR controller setting
+//*===========================================
+// CTL setting
+	ldr r0, =DATABAHN_BASE_ADDR
+
+#if defined(CONFIG_ZQ_CALIB)
+	do_zq_calib
+#else
+// setmem /32 0x1400012C = 0x00000817  // pd=<<8, pu=<<0
+	ldr r1, =0x00000817
+	str r1, [r0, #0x12c]
+// setmem /32 0x14000128 = 0x09180000  // (pd+1)<<24, (pu+1)<<16
+	ldr r1, =0x09180000
+	str r1, [r0, #0x128]
+// load PU, pu_pd_sel=0
+// setmem /32 0x14000124 = 0x00310000  // software load ZQ: 3<<20, 1<<16
+	ldr r1, =0x00310000
+	str r1, [r0, #0x124]
+// setmem /32 0x14000124 = 0x00200000  // clear for next load
+	ldr r1, =0x00200000
+	str r1, [r0, #0x124]
+// load PD, pu_pd_sel=1
+// setmem /32 0x14000128 = 0x09180010  // (pd+1)<<24, (pu+1)<<16, 1<<4
+	ldr r1, =0x09180010
+	str r1, [r0, #0x128]
+// setmem /32 0x14000124 = 0x00310000  // software load ZQ: 3<<20, 1<<16
+	ldr r1, =0x00310000
+	str r1, [r0, #0x124]
+// setmem /32 0x14000124 = 0x00200000  // clear for next load
+	ldr r1, =0x00200000
+	str r1, [r0, #0x124]
+#endif
+
+/*	CTL setting */
+/*	setmem /32 0x14000000    = 0x00000400 */
+	ldr r1, =0x00000400
+	str r1, [r0, #0x0]
+/*	setmem /32 0x14000004    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4]
+/*	setmem /32 0x14000008    = 0x0000d056  */
+	ldr r1, =0x0000d056
+	str r1, [r0, #0x8]
+/*	setmem /32 0x1400000c    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0xc]
+/*	setmem /32 0x14000010    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x10]
+/*	setmem /32 0x14000014    = 0x02000000 */
+	ldr r1, =0x02000000
+	str r1, [r0, #0x14]
+/*	setmem /32 0x14000018    = 0x02030808 */
+	ldr r1, =0x02030808
+	str r1, [r0, #0x18]
+/*	setmem /32 0x1400001c    = 0x0c100302 */
+	ldr r1, =0x0c100302
+	str r1, [r0, #0x1c]
+/*	setmem /32 0x14000020    = 0x02020402 */
+	ldr r1, =0x02020402
+	str r1, [r0, #0x20]
+/*	setmem /32 0x14000024    = 0x0048eb04 */
+	ldr r1, =0x0048eb04
+	str r1, [r0, #0x24]
+/*	setmem /32 0x14000028    = 0x01000303 */
+	ldr r1, =0x01000303
+	str r1, [r0, #0x28]
+/*	setmem /32 0x1400002c    = 0x08040401 */
+	ldr r1, =0x08040401
+	str r1, [r0, #0x2c]
+/*	setmem /32 0x14000030    = 0x000000c8 */
+	ldr r1, =0x000000c8
+	str r1, [r0, #0x30]
+/*	setmem /32 0x14000034    = 0x006b0c02 */
+	ldr r1, =0x006b0c02
+	str r1, [r0, #0x34]
+/*	setmem /32 0x14000038    = 0x00000005 */
+	ldr r1, =0x00000005
+	str r1, [r0, #0x38]
+/*	setmem /32 0x1400003c    = 0x00003401 */
+	ldr r1, =0x00003401
+	str r1, [r0, #0x3c]
+/*	setmem /32 0x14000040    = 0x0005081b */
+	ldr r1, =0x0005081b
+	str r1, [r0, #0x40]
+/*	setmem /32 0x14000044    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x44]
+/*	setmem /32 0x14000048    = 0x003700c8 */
+	ldr r1, =0x003700c8
+	str r1, [r0, #0x48]
+/*	setmem /32 0x1400004c    = 0x00010000 */
+	ldr r1, =0x00010000
+	str r1, [r0, #0x4c]
+/*	setmem /32 0x14000050    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x50]
+/*	setmem /32 0x14000054    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x54]
+/*	setmem /32 0x14000058    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x58]
+/*	setmem /32 0x1400005c    = 0x03000000 */
+	ldr r1, =0x03000000
+	str r1, [r0, #0x5c]
+/*	setmem /32 0x14000060    = 0x00000003 */
+	ldr r1, =0x00000003
+	str r1, [r0, #0x60]
+/*	setmem /32 0x14000064    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x64]
+/*	setmem /32 0x14000068    = 0x06420000 */
+	ldr r1, =0x06420000
+	str r1, [r0, #0x68]
+/*	setmem /32 0x1400006c    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x6c]
+/*	setmem /32 0x14000070    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x70]
+/*	setmem /32 0x14000074    = 0x06420000 */
+	ldr r1, =0x06420000
+	str r1, [r0, #0x74]
+/*	setmem /32 0x14000078    = 0x00000004 */
+	ldr r1, =0x00000004
+	str r1, [r0, #0x78]
+/*	setmem /32 0x1400007c    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x7c]
+/*	setmem /32 0x14000080    = 0x02000000 */
+	ldr r1, =0x02000000
+	str r1, [r0, #0x80]
+/*	setmem /32 0x14000084    = 0x00000100 */
+	ldr r1, =0x00000100
+	str r1, [r0, #0x84]
+/*	setmem /32 0x14000088    = 0x02400040 */
+	ldr r1, =0x02400040
+	str r1, [r0, #0x88]
+/*	setmem /32 0x1400008c    = 0x01000000 */
+	ldr r1, =0x01000000
+	str r1, [r0, #0x8c]
+/*	setmem /32 0x14000090    = 0x0a000101 */
+	ldr r1, =0x0a000101
+	str r1, [r0, #0x90]
+/*	setmem /32 0x14000094    = 0x01011f1f */
+	ldr r1, =0x01011f1f
+	str r1, [r0, #0x94]
+/*	setmem /32 0x14000098    = 0x01010101 */
+	ldr r1, =0x01010101
+	str r1, [r0, #0x98]
+/*	setmem /32 0x1400009c    = 0x00030103 */
+	ldr r1, =0x00030103
+	str r1, [r0, #0x9c]
+/*	setmem /32 0x140000a0    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0xa0]
+/*	setmem /32 0x140000a4    = 0x00010000 */
+	ldr r1, =0x00010000
+	str r1, [r0, #0xa4]
+/*	setmem /32 0x140000a8    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0xa8]
+/*	setmem /32 0x140000ac    = 0x0000ffff */
+	ldr r1, =0x0000ffff
+	str r1, [r0, #0xac]
+/*	setmem /32 0x140000b0    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0xb0]
+/*	setmem /32 0x140000b4    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0xb4]
+/*	setmem /32 0x140000b8    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0xb8]
+/*	setmem /32 0x140000bc    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0xbc]
+/*	setmem /32 0x140000c0    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0xc0]
+/*	setmem /32 0x140000c4    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0xc4]
+/*	setmem /32 0x140000c8    = 0x02020101 */
+	ldr r1, =0x02020101
+	str r1, [r0, #0xc8]
+/*	setmem /32 0x140000cc    = 0x01000000 */
+	ldr r1, =0x01000000
+	str r1, [r0, #0xcc]
+/*	setmem /32 0x140000d0    = 0x01010201 */
+	ldr r1, =0x01010201
+	str r1, [r0, #0xd0]
+/*	setmem /32 0x140000d4    = 0x00000200 */
+	ldr r1, =0x00000200
+	str r1, [r0, #0xd4]
+/*	setmem /32 0x140000d8    = 0x00000101 */
+	ldr r1, =0x00000101
+	str r1, [r0, #0xd8]
+/*	setmem /32 0x140000dc    = 0x0003ffff */
+	ldr r1, =0x0003ffff
+	str r1, [r0, #0xdc]
+/*	setmem /32 0x140000e0    = 0x0000ffff */
+	ldr r1, =0x0000ffff
+	str r1, [r0, #0xe0]
+/*	setmem /32 0x140000e4    = 0x02020000 */
+	ldr r1, =0x02020000
+	str r1, [r0, #0xe4]
+/*	setmem /32 0x140000e8    = 0x02020202 */
+	ldr r1, =0x02020202
+	str r1, [r0, #0xe8]
+/*	setmem /32 0x140000ec    = 0x00000202 */
+	ldr r1, =0x00000202
+	str r1, [r0, #0xec]
+/*	setmem /32 0x140000f0    = 0x01010064 */
+	ldr r1, =0x01010064
+	str r1, [r0, #0xf0]
+/*	setmem /32 0x140000f4    = 0x01010101 */
+	ldr r1, =0x01010101
+	str r1, [r0, #0xf4]
+/*	setmem /32 0x140000f8    = 0x00010101 */
+	ldr r1, =0x00010101
+	str r1, [r0, #0xf8]
+/*	setmem /32 0x140000fc    = 0x00000064 */
+	ldr r1, =0x00000064
+	str r1, [r0, #0xfc]
+/*	setmem /32 0x14000100    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x100]
+/*	setmem /32 0x14000104    = 0x02000702 */
+	ldr r1, =0x02000702
+	str r1, [r0, #0x104]
+/*	setmem /32 0x14000108    = 0x081b0000 */
+	ldr r1, =0x081b0000
+	str r1, [r0, #0x108]
+/*	setmem /32 0x1400010c    = 0x081b081b */
+	ldr r1, =0x081b081b
+	str r1, [r0, #0x10c]
+/*	setmem /32 0x14000110    = 0x081b081b */
+	ldr r1, =0x081b081b
+	str r1, [r0, #0x110]
+/*	setmem /32 0x14000114    = 0x0304081b */
+	ldr r1, =0x0304081b
+	str r1, [r0, #0x114]
+/*	setmem /32 0x14000118    = 0x01010002 */
+	ldr r1, =0x01010002
+	str r1, [r0, #0x118]
+/*	setmem /32 0x1400011c    = 0x00001000 */
+	ldr r1, =0x00001000
+	str r1, [r0, #0x11c]
+/*	setmem /32 0x14000120    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x120]
+/*	setmem /32 0x14000124    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x124]
+/*	setmem /32 0x14000128    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x128]
+/*	setmem /32 0x1400012c    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x12c]
+/*	setmem /32 0x14000130    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x130]
+/*	setmem /32 0x14000134    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x134]
+/*	setmem /32 0x14000138    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x138]
+/*	setmem /32 0x1400013c    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x13c]
+/*	setmem /32 0x14000140    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x140]
+/*	setmem /32 0x14000144    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x144]
+/*	setmem /32 0x14000148    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x148]
+/*	setmem /32 0x1400014c    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x14c]
+/*	setmem /32 0x14000150    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x150]
+/*	setmem /32 0x14000154    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x154]
+/*	setmem /32 0x14000158    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x158]
+
+/*	PHY setting */
+/*	setmem /32 0x14000200    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x200]
+/*	setmem /32 0x14000204    = 0x000f1100 */
+	ldr r1, =0x000f1100
+	str r1, [r0, #0x204]
+/*	setmem /32 0x14000208    = 0xf4013a27 */
+	ldr r1, =0xf4013a27
+	str r1, [r0, #0x208]
+/*	setmem /32 0x1400020c    = 0x26c002c0 */
+	ldr r1, =0x26c002c0
+	str r1, [r0, #0x20c]
+/*	setmem /32 0x14000210    = 0xf4013a27 */
+	ldr r1, =0xf4013a27
+	str r1, [r0, #0x210]
+/*	setmem /32 0x14000214    = 0x26c002c0 */
+	ldr r1, =0x26c002c0
+	str r1, [r0, #0x214]
+/*	setmem /32 0x14000218    = 0xf4013a27 */
+	ldr r1, =0xf4013a27
+	str r1, [r0, #0x218]
+/*	setmem /32 0x1400021c    = 0x26c002c0 */
+	ldr r1, =0x26c002c0
+	str r1, [r0, #0x21c]
+/*	setmem /32 0x14000220    = 0xf4013a27 */
+	ldr r1, =0xf4013a27
+	str r1, [r0, #0x220]
+/*	setmem /32 0x14000224    = 0x26c002c0 */
+	ldr r1, =0x26c002c0
+	str r1, [r0, #0x224]
+/*	setmem /32 0x14000228    = 0xf4013a27 */
+	ldr r1, =0xf4013a27
+	str r1, [r0, #0x228]
+/*	setmem /32 0x1400022c    = 0x26c002c0 */
+	ldr r1, =0x26c002c0
+	str r1, [r0, #0x22c]
+/*	setmem /32 0x14000230    = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x230]
+/*	setmem /32 0x14000234    = 0x00000005 */
+	ldr r1, =0x00000005
+	str r1, [r0, #0x234]
+/*	setmem /32 0x14000238    = 0x20099d14 */
+	ldr r1, =0x20099d14
+	str r1, [r0, #0x238]
+/*	setmem /32 0x1400023c    = 0x000a1f01 */
+	ldr r1, =0x000a1f01
+	str r1, [r0, #0x23c]
+/*	setmem /32 0x14000240    = 0x20099d14 */
+	ldr r1, =0x20099d14
+	str r1, [r0, #0x240]
+/*	setmem /32 0x14000244    = 0x000a1f01 */
+	ldr r1, =0x000a1f01
+	str r1, [r0, #0x244]
+/*	setmem /32 0x14000248    = 0x20099d14 */
+	ldr r1, =0x20099d14
+	str r1, [r0, #0x248]
+/*	setmem /32 0x1400024c    = 0x000a1f01 */
+	ldr r1, =0x000a1f01
+	str r1, [r0, #0x24c]
+/*	setmem /32 0x14000250    = 0x20099d14 */
+	ldr r1, =0x20099d14
+	str r1, [r0, #0x250]
+/*	setmem /32 0x14000254    = 0x000a1f01 */
+	ldr r1, =0x000a1f01
+	str r1, [r0, #0x254]
+/*	setmem /32 0x14000258    = 0x20099d14 */
+	ldr r1, =0x20099d14
+	str r1, [r0, #0x258]
+/*	setmem /32 0x1400025c    = 0x000a1f01 */
+	ldr r1, =0x000a1f01
+	str r1, [r0, #0x25c]
+
+/*	Start ddr */
+/*	setmem /32 0x14000000 = 0x00000401  // bit[0]: start */
+	ldr	r1, =0x00000401
+	str	r1, [r0, #0x0]
+
+/*	poll to make sure it is done */
+1:
+	ldr	r1, [r0, #0xa8]
+	ands	r1, r1, #0x10
+	beq	1b
+
+#else
+
+/*==================================================================
+ * lpddr1-mddr
+ *=================================================================*/
+
+/* DDR clock setting -- Set DDR to be div 4 to get 200MHz */
+/* setmem /32 0x53FD4098 = 0x80000004 */
+	ldr r1, =0x80000004
+	str r1, [r0, #0x98]
+
+/* poll to make sure DDR dividers take effect */
+1:
+    ldr r1, [r0, #0x8c]
+    ands r1, r1, #0x4
+    bne 1b
+
+/*==================================================================
+ * IOMUX
+ *=================================================================*/
+	ldr r0, =0x53fa8600
+	mov r1, #0x00000000
+	mov r3, #0x00380000
+	mov r2, #0x0
+	str r1, [r0, #0xac]
+	str r2, [r0, #0x6c]
+	str r2, [r0, #0x8c]
+	str r2, [r0, #0x70]
+	str r3, [r0, #0xa4]
+	str r3, [r0, #0x68]
+	str r3, [r0, #0x98]
+	str r3, [r0, #0xa0]
+	str r3, [r0, #0xa8]
+	str r3, [r0, #0xb4]
+
+	ldr r0, =0x53fa8400
+	str r3, [r0, #0x98]
+	str r3, [r0, #0x9c]
+	str r3, [r0, #0xf0]
+	str r3, [r0, #0x100]
+	str r3, [r0, #0xc8]
+	str r3, [r0, #0x128]
+	str r3, [r0, #0xf4]
+	str r3, [r0, #0xfc]
+	str r3, [r0, #0xcc]
+	str r3, [r0, #0x124]
+
+//*===========================================
+//   DDR controller setting
+//*===========================================
+// CTL setting
+	ldr r0, =DATABAHN_BASE_ADDR
+
+#if defined(CONFIG_ZQ_CALIB)
+	do_zq_calib
+#else
+// setmem /32 0x1400012C = 0x00000817  // pd=<<8, pu=<<0
+	ldr r1, =0x00000817
+	str r1, [r0, #0x12c]
+// setmem /32 0x14000128 = 0x09180000  // (pd+1)<<24, (pu+1)<<16
+	ldr r1, =0x09180000
+	str r1, [r0, #0x128]
+// load PU, pu_pd_sel=0
+// setmem /32 0x14000124 = 0x00310000  // software load ZQ: 3<<20, 1<<16
+	ldr r1, =0x00310000
+	str r1, [r0, #0x124]
+// setmem /32 0x14000124 = 0x00200000  // clear for next load
+	ldr r1, =0x00200000
+	str r1, [r0, #0x124]
+// load PD, pu_pd_sel=1
+// setmem /32 0x14000128 = 0x09180010  // (pd+1)<<24, (pu+1)<<16, 1<<4
+	ldr r1, =0x09180010
+	str r1, [r0, #0x128]
+// setmem /32 0x14000124 = 0x00310000  // software load ZQ: 3<<20, 1<<16
+	ldr r1, =0x00310000
+	str r1, [r0, #0x124]
+// setmem /32 0x14000124 = 0x00200000  // clear for next load
+	ldr r1, =0x00200000
+	str r1, [r0, #0x124]
+#endif
+
+/*==============================================================
+ *  DDR setting
+ *=============================================================*/
+/* setmem /32 0x14000000 = 0x00000100 */
+	ldr r1, =0x00000100
+	str r1, [r0, #0x0]
+/* setmem /32 0x14000008 = 0x00009c40 */
+	ldr r1, =0x00009c40
+	str r1, [r0, #0x8]
+/* setmem /32 0x14000014 = 0x02000000 */
+	ldr r1, =0x02000000
+	str r1, [r0, #0x14]
+/* setmem /32 0x14000018 = 0x01010706 */
+	ldr r1, =0x01010706
+	str r1, [r0, #0x018]
+/* setmem /32 0x1400001c = 0x080b0201 */
+	ldr r1, =0x080b0201
+	str r1, [r0, #0x01c]
+/* setmem /32 0x14000020 = 0x02000303 */
+	ldr r1, =0x02000303
+	str r1, [r0, #0x020]
+/* setmem /32 0x14000024 = 0x0136b002 */
+	ldr r1, =0x0136b002
+	str r1, [r0, #0x024]
+/* setmem /32 0x14000028 = 0x01000101 */
+	ldr r1, =0x01000101
+	str r1, [r0, #0x028]
+/* setmem /32 0x1400002c = 0x06030301 */
+	ldr r1, =0x06030301
+	str r1, [r0, #0x02c]
+/* setmem /32 0x14000030 = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x030]
+/* setmem /32 0x14000034 = 0x00000a02 */
+	ldr r1, =0x00000a02
+	str r1, [r0, #0x034]
+/* setmem /32 0x14000038 = 0x00000003 */
+	ldr r1, =0x00000003
+	str r1, [r0, #0x038]
+/* setmem /32 0x1400003c = 0x00001401 */
+	ldr r1, =0x00001401
+	str r1, [r0, #0x03c]
+/* setmem /32 0x14000040 = 0x0005030f */
+	ldr r1, =0x0005030f
+	str r1, [r0, #0x040]
+/* setmem /32 0x14000044 = 0x00000200 */
+	ldr r1, =0x00000200
+	str r1, [r0, #0x044]
+/* setmem /32 0x14000048 = 0x00180018 */
+	ldr r1, =0x00180018
+	str r1, [r0, #0x048]
+/* setmem /32 0x1400004c = 0x00010000 */
+	ldr r1, =0x00010000
+	str r1, [r0, #0x04c]
+/* setmem /32 0x1400005c = 0x01000000 */
+	ldr r1, =0x01000000
+	str r1, [r0, #0x05c]
+/* setmem /32 0x14000060 = 0x00000001 */
+	ldr r1, =0x00000001
+	str r1, [r0, #0x060]
+/* setmem /32 0x14000064 = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x064]
+/* setmem /32 0x14000068 = 0x00320000 */
+	ldr r1, =0x00320000
+	str r1, [r0, #0x068]
+/* setmem /32 0x1400006c = 0x00800000 */
+	ldr r1, =0x00800000
+	str r1, [r0, #0x06c]
+/* setmem /32 0x14000070 = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x070]
+/* setmem /32 0x14000074 = 0x00320000 */
+	ldr r1, =0x00320000
+	str r1, [r0, #0x074]
+/* setmem /32 0x14000080 = 0x02000000 */
+	ldr r1, =0x02000000
+	str r1, [r0, #0x080]
+/* setmem /32 0x14000084 = 0x00000100 */
+	ldr r1, =0x00000100
+	str r1, [r0, #0x084]
+/* setmem /32 0x14000088 = 0x02400040 */
+	ldr r1, =0x02400040
+	str r1, [r0, #0x088]
+/* setmem /32 0x1400008c = 0x01000000 */
+	ldr r1, =0x01000000
+	str r1, [r0, #0x08c]
+/* setmem /32 0x14000090 = 0x0a000100 */
+	ldr r1, =0x0a000100
+	str r1, [r0, #0x090]
+/* setmem /32 0x14000094 = 0x01011f1f */
+	ldr r1, =0x01011f1f
+	str r1, [r0, #0x094]
+/* setmem /32 0x14000098 = 0x01010101 */
+	ldr r1, =0x01010101
+	str r1, [r0, #0x098]
+/* setmem /32 0x1400009c = 0x00030101 */
+	ldr r1, =0x00030101
+	str r1, [r0, #0x09c]
+/* setmem /32 0x140000a4 = 0x00010000 */
+	ldr r1, =0x00010000
+	str r1, [r0, #0x0a4]
+/* setmem /32 0x140000ac = 0x0000ffff */
+	ldr r1, =0x0000ffff
+	str r1, [r0, #0x0ac]
+/* setmem /32 0x140000c8 = 0x02020101 */
+	ldr r1, =0x02020101
+	str r1, [r0, #0x0c8]
+/* setmem /32 0x140000cc = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x0cc]
+/* setmem /32 0x140000d0 = 0x01000202 */
+	ldr r1, =0x01000202
+	str r1, [r0, #0x0d0]
+/* setmem /32 0x140000d4 = 0x02030302 */
+	ldr r1, =0x02030302
+	str r1, [r0, #0x0d4]
+/*  setmem /32 0x140000d8 = 0x00000001 */
+	ldr r1, =0x00000001
+	str r1, [r0, #0x0d8]
+/* setmem /32 0x140000dc = 0x0000ffff */
+	ldr r1, =0x0000ffff
+	str r1, [r0, #0x0dc]
+/* setmem /32 0x140000e0 = 0x0000ffff */
+	ldr r1, =0x0000ffff
+	str r1, [r0, #0x0e0]
+/* setmem /32 0x140000e4 = 0x02020000 */
+	ldr r1, =0x02020000
+	str r1, [r0, #0x0e4]
+/* setmem /32 0x140000e8 = 0x02020202 */
+	ldr r1, =0x02020202
+	str r1, [r0, #0x0e8]
+/* setmem /32 0x140000ec = 0x00000202 */
+	ldr r1, =0x00000202
+	str r1, [r0, #0x0ec]
+/* setmem /32 0x140000f0 = 0x01010064 */
+	ldr r1, =0x01010064
+	str r1, [r0, #0x0f0]
+/* setmem /32 0x140000f4 = 0x01010101 */
+	ldr r1, =0x01010101
+	str r1, [r0, #0x0f4]
+/* setmem /32 0x140000f8 = 0x00010101 */
+	ldr r1, =0x00010101
+	str r1, [r0, #0x0f8]
+/* setmem /32 0x140000fc = 0x00000064 */
+	ldr r1, =0x00000064
+	str r1, [r0, #0x0fc]
+/* setmem /32 0x14000104 = 0x02000602 */
+	ldr r1, =0x02000602
+	str r1, [r0, #0x0104]
+/* setmem /32 0x14000108 = 0x06120000 */
+	ldr r1, =0x06120000
+	str r1, [r0, #0x0108]
+/* setmem /32 0x1400010c = 0x06120612 */
+	ldr r1, =0x06120612
+	str r1, [r0, #0x010c]
+/* setmem /32 0x14000110 = 0x06120612 */
+	ldr r1, =0x06120612
+	str r1, [r0, #0x0110]
+/* setmem /32 0x14000114 = 0x01030612 */
+	ldr r1, =0x01030612
+	str r1, [r0, #0x0114]
+/* setmem /32 0x14000118 = 0x01010002 */
+	ldr r1, =0x01010002
+	str r1, [r0, #0x0118]
+
+/*=============================================================
+ *  DDR PHY setting
+ *===========================================================*/
+
+/* setmem /32 0x14000200 = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x200]
+/* setmem /32 0x14000204 = 0x00000000 */
+	str r1, [r0, #0x0204]
+/* setmem /32 0x14000208 = 0xf5002725 */
+	ldr r1, =0xf5002725
+	str r1, [r0, #0x0208]
+/* setmem /32 0x14000210 = 0xf5002725 */
+	str r1, [r0, #0x210]
+/* setmem /32 0x14000218 = 0xf5002725 */
+	str r1, [r0, #0x218]
+/* setmem /32 0x14000220 = 0xf5002725 */
+	str r1, [r0, #0x0220]
+/* setmem /32 0x14000228 = 0xf5002725 */
+	str r1, [r0, #0x0228]
+/* setmem /32 0x14000234 = 0x00800006*/
+	ldr r1, =0x00800006
+	str r1, [r0, #0x0234]
+/* setmem /32 0x1400020c = 0x070002d0 */
+	ldr r1, =0x070002d0
+	str r1, [r0, #0x020c]
+/* setmem /32 0x14000214 = 0x074002d0 */
+	str r1, [r0, #0x0214]
+/* setmem /32 0x1400021c = 0x074002d0 */
+	str r1, [r0, #0x021c]
+/* setmem /32 0x14000224 = 0x074002d0 */
+	str r1, [r0, #0x0224]
+/* setmem /32 0x1400022c = 0x074002d0 */
+	str r1, [r0, #0x022c]
+/* setmem /32 0x14000230 = 0x00000000 */
+	ldr r1, =0x00000000
+	str r1, [r0, #0x0230]
+/* setmem /32 0x14000238 = 0x200e1014 */
+	ldr r1, =0x200e1014
+	str r1, [r0, #0x0238]
+/* setmem /32 0x14000240 = 0x200e1014 */
+	str r1, [r0, #0x0240]
+/* setmem /32 0x14000248 = 0x200e1014 */
+	str r1, [r0, #0x0248]
+/* setmem /32 0x14000250 = 0x200e1014 */
+	str r1, [r0, #0x0250]
+/* setmem /32 0x14000258 = 0x200e1014 */
+	str r1, [r0, #0x0258]
+/* setmem /32 0x1400023c = 0x000d9f01 */
+	ldr r1, =0x000d9f01
+	str r1, [r0, #0x023c]
+/* setmem /32 0x14000244 = 0x000d9f01 */
+	str r1, [r0, #0x0244]
+/* setmem /32 0x1400024c = 0x000d9f01 */
+	str r1, [r0, #0x024c]
+/* setmem /32 0x14000254 = 0x000d9f01 */
+	str r1, [r0, #0x0254]
+/* setmem /32 0x1400025c = 0x000d9f01 */
+	str r1, [r0, #0x025c]
+
+/* Start ddr */
+/* setmem /32 0x14000000 = 0x00000101  // bit[0]: start */
+	ldr r1, =0x00000101
+	str r1, [r0, #0x0]
 /* poll to make sure it is done */
 1:
 	ldr r1, [r0, #0xa8]
 	ands r1, r1, #0x10
 	beq 1b
 
+#endif
+
 /*
  * The following is to fill in those arguments for this ROM function
  * pu_irom_hwcnfg_setup(void **start, size_t *bytes, const void *boot_data)
@@ -748,11 +1783,12 @@ after_calling_rom___pu_irom_hwcnfg_setup:
 	mov r0, #1
 	bx lr          /* return back to ROM code */
 
+/* Data be copied by pu_irom_hwcnfg_setup() */
 DDR_DEST_ADDR:		.word TEXT_BASE
 COPY_SIZE:		.word _end - TEXT_BASE
 BOOT_DATA:		.word TEXT_BASE
 			.word _end - TEXT_BASE
 			.word 0
-IVT2_HDR_OFS:		.word ivt2_header - TEXT_BASE
+IVT2_HDR_OFS:           .word ivt2_header - TEXT_BASE
 
 #endif
diff --git a/board/freescale/mx50_rdp/mx50_rdp.c b/board/freescale/mx50_rdp/mx50_rdp.c
index 924c7e6..6450373 100644
--- a/board/freescale/mx50_rdp/mx50_rdp.c
+++ b/board/freescale/mx50_rdp/mx50_rdp.c
@@ -52,11 +52,14 @@
 #include <asm/clock.h>
 #endif
 
+#ifdef CONFIG_MXC_EPDC
+#include <lcd.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static u32 system_rev;
 static enum boot_device boot_dev;
-u32	mx51_io_base_addr;
 
 static inline void setup_boot_device(void)
 {
@@ -261,6 +264,25 @@ static void setup_i2c(unsigned int module_base)
 				PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
 				PAD_CTL_HYS_ENABLE);
 		break;
+	case I2C3_BASE_ADDR:
+		/* i2c3 SDA */
+		mxc_request_iomux(MX50_PIN_I2C3_SDA,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_pad(MX50_PIN_I2C3_SDA,
+				PAD_CTL_SRE_FAST |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE |
+				PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+				PAD_CTL_HYS_ENABLE);
+
+		/* i2c3 SCL */
+		mxc_request_iomux(MX50_PIN_I2C3_SCL,
+				IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+		mxc_iomux_set_pad(MX50_PIN_I2C3_SCL,
+				PAD_CTL_SRE_FAST |
+				PAD_CTL_ODE_OPENDRAIN_ENABLE |
+				PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+				PAD_CTL_HYS_ENABLE);
+		break;
 	default:
 		printf("Invalid I2C base: 0x%x\n", module_base);
 		break;
@@ -566,6 +588,7 @@ static void setup_fec(void)
 {
 	volatile unsigned int reg;
 
+#if defined(CONFIG_MX50_RDP)
 	/* FEC_EN: gpio6-23 set to 0 to enable FEC */
 	mxc_request_iomux(MX50_PIN_I2C3_SDA, IOMUX_CONFIG_ALT1);
 
@@ -576,7 +599,7 @@ static void setup_fec(void)
 	reg = readl(GPIO6_BASE_ADDR + 0x4);
 	reg |= (1 << 23);
 	writel(reg, GPIO6_BASE_ADDR + 0x4);
-
+#endif
 
 	/*FEC_MDIO*/
 	mxc_request_iomux(MX50_PIN_SSI_RXC, IOMUX_CONFIG_ALT6);
@@ -624,6 +647,7 @@ static void setup_fec(void)
 	mxc_iomux_set_pad(MX50_PIN_DISP_D2, 0x0);
 	mxc_iomux_set_input(MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, 0);
 
+#if defined(CONFIG_MX50_RDP)
 	/* FEC_RESET_B: gpio4-12 */
 	mxc_request_iomux(MX50_PIN_ECSPI1_SCLK, IOMUX_CONFIG_ALT1);
 
@@ -640,6 +664,26 @@ static void setup_fec(void)
 	reg = readl(GPIO4_BASE_ADDR + 0x0);
 	reg |= (1 << 12);
 	writel(reg, GPIO4_BASE_ADDR + 0x0);
+#elif defined(CONFIG_MX50_ARM2)
+	/* phy reset: gpio4-6 */
+	mxc_request_iomux(MX50_PIN_KEY_COL3, IOMUX_CONFIG_ALT1);
+
+	reg = readl(GPIO4_BASE_ADDR + 0x0);
+	reg &= ~0x40;
+	writel(reg, GPIO4_BASE_ADDR + 0x0);
+
+	reg = readl(GPIO4_BASE_ADDR + 0x4);
+	reg |= 0x40;
+	writel(reg, GPIO4_BASE_ADDR + 0x4);
+
+	udelay(500);
+
+	reg = readl(GPIO4_BASE_ADDR + 0x0);
+	reg |= 0x40;
+	writel(reg, GPIO4_BASE_ADDR + 0x0);
+#else
+#	error "Unsupported board!"
+#endif
 }
 #endif
 
@@ -772,6 +816,244 @@ int board_mmc_init(bd_t *bis)
 
 #endif
 
+#ifdef CONFIG_MXC_EPDC
+#ifdef CONFIG_SPLASH_SCREEN
+int setup_splash_img()
+{
+#ifdef CONFIG_SPLASH_IS_IN_MMC
+	int mmc_dev = get_mmc_env_devno();
+	ulong offset = CONFIG_SPLASH_IMG_OFFSET;
+	ulong size = CONFIG_SPLASH_IMG_SIZE;
+	ulong addr = 0;
+	char *s = NULL;
+	struct mmc *mmc = find_mmc_device(mmc_dev);
+	uint blk_start, blk_cnt, n;
+
+	s = getenv("splashimage");
+
+	if (NULL == s) {
+		puts("env splashimage not found!\n");
+		return -1;
+	}
+	addr = simple_strtoul(s, NULL, 16);
+
+	if (!mmc) {
+		printf("MMC Device %d not found\n",
+			mmc_dev);
+		return -1;
+	}
+
+	if (mmc_init(mmc)) {
+		puts("MMC init failed\n");
+		return  -1;
+	}
+
+	blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
+	blk_cnt   = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
+	n = mmc->block_dev.block_read(mmc_dev, blk_start,
+					blk_cnt, (u_char *)addr);
+	flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
+
+	return (n == blk_cnt) ? 0 : -1;
+#endif
+}
+#endif
+
+vidinfo_t panel_info = {
+	.vl_refresh = 60,
+	.vl_col = 800,
+	.vl_row = 600,
+	.vl_pixclock = 17700000,
+	.vl_left_margin = 8,
+	.vl_right_margin = 142,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 10,
+	.vl_hsync = 20,
+	.vl_vsync = 4,
+	.vl_sync = 0,
+	.vl_mode = 0,
+	.vl_flag = 0,
+	.vl_bpix = 3,
+	cmap:0,
+};
+
+static void setup_epdc_power()
+{
+	unsigned int reg;
+
+	/* Setup epdc voltage */
+
+	/* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */
+	mxc_request_iomux(MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1);
+
+	/* EPDC VCOM0 - GPIO4[21] for VCOM control */
+	mxc_request_iomux(MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1);
+	/* Set as output */
+	reg = readl(GPIO4_BASE_ADDR + 0x4);
+	reg |= (1 << 21);
+	writel(reg, GPIO4_BASE_ADDR + 0x4);
+
+	/* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */
+	mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1);
+	/* Set as output */
+	reg = readl(GPIO6_BASE_ADDR + 0x4);
+	reg |= (1 << 16);
+	writel(reg, GPIO6_BASE_ADDR + 0x4);
+}
+
+void epdc_power_on()
+{
+	unsigned int reg;
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	reg = readl(GPIO6_BASE_ADDR + 0x0);
+	reg |= (1 << 16);
+	writel(reg, GPIO6_BASE_ADDR + 0x0);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(GPIO3_BASE_ADDR + 0x0);
+		if (!(reg & (1 << 28)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	reg = readl(GPIO4_BASE_ADDR + 0x0);
+	reg |= (1 << 21);
+	writel(reg, GPIO4_BASE_ADDR + 0x0);
+
+	reg = readl(GPIO4_BASE_ADDR + 0x0);
+
+	udelay(500);
+}
+
+void  epdc_power_off()
+{
+	unsigned int reg;
+	/* Set PMIC Wakeup to low - disable Display power */
+	reg = readl(GPIO6_BASE_ADDR + 0x0);
+	reg |= 0 << 16;
+	writel(reg, GPIO6_BASE_ADDR + 0x0);
+
+	/* Disable VCOM */
+	reg = readl(GPIO4_BASE_ADDR + 0x0);
+	reg |= 0 << 21;
+	writel(reg, GPIO4_BASE_ADDR + 0x0);
+}
+
+int setup_waveform_file()
+{
+#ifdef CONFIG_WAVEFORM_FILE_IN_MMC
+	int mmc_dev = get_mmc_env_devno();
+	ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
+	ulong size = CONFIG_WAVEFORM_FILE_SIZE;
+	ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
+	char *s = NULL;
+	struct mmc *mmc = find_mmc_device(mmc_dev);
+	uint blk_start, blk_cnt, n;
+
+	if (!mmc) {
+		printf("MMC Device %d not found\n",
+			mmc_dev);
+		return -1;
+	}
+
+	if (mmc_init(mmc)) {
+		puts("MMC init failed\n");
+		return -1;
+	}
+
+	blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
+	blk_cnt   = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
+	n = mmc->block_dev.block_read(mmc_dev, blk_start,
+		blk_cnt, (u_char *)addr);
+	flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
+
+	return (n == blk_cnt) ? 0 : -1;
+#else
+	return -1;
+#endif
+}
+
+static void setup_epdc()
+{
+	unsigned int reg;
+
+	/* epdc iomux settings */
+	mxc_request_iomux(MX50_PIN_EPDC_D0, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_D1, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_D2, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_D3, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_D4, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_D5, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_D6, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_D7, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_GDCLK, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_GDSP, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_GDOE, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_GDRL, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_SDCLK, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_SDOE, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_SDLE, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_SDSHR, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_BDR0, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_SDCE0, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_SDCE1, IOMUX_CONFIG_ALT0);
+	mxc_request_iomux(MX50_PIN_EPDC_SDCE2, IOMUX_CONFIG_ALT0);
+
+
+	/*** epdc Maxim PMIC settings ***/
+
+	/* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */
+	mxc_request_iomux(MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1);
+
+	/* EPDC VCOM0 - GPIO4[21] for VCOM control */
+	mxc_request_iomux(MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1);
+
+	/* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */
+	mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1);
+
+
+	/*** Set pixel clock rates for EPDC ***/
+
+	/* EPDC AXI clk and EPDC PIX clk from PLL1 */
+	reg = readl(CCM_BASE_ADDR + CLKCTL_CLKSEQ_BYPASS);
+	reg &= ~(0x3 << 4);
+	reg |= (0x2 << 4) | (0x2 << 12);
+	writel(reg, CCM_BASE_ADDR + CLKCTL_CLKSEQ_BYPASS);
+
+	/* EPDC AXI clk enable and set to 200MHz (800/4) */
+	reg = readl(CCM_BASE_ADDR + 0xA8);
+	reg &= ~((0x3 << 30) | 0x3F);
+	reg |= (0x2 << 30) | 0x4;
+	writel(reg, CCM_BASE_ADDR + 0xA8);
+
+	/* EPDC PIX clk enable and set to 20MHz (800/40) */
+	reg = readl(CCM_BASE_ADDR + 0xA0);
+	reg &= ~((0x3 << 30) | (0x3 << 12) | 0x3F);
+	reg |= (0x2 << 30) | (0x1 << 12) | 0x2D;
+	writel(reg, CCM_BASE_ADDR + 0xA0);
+
+	panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR;
+	panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR;
+
+	panel_info.epdc_data.wv_modes.mode_init = 0;
+	panel_info.epdc_data.wv_modes.mode_du = 1;
+	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
+	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
+
+	setup_epdc_power();
+
+	/* Assign fb_base */
+	gd->fb_base = CONFIG_FB_BASE;
+}
+#endif
+
+
 #ifdef CONFIG_IMX_CSPI
 static void setup_power(void)
 {
@@ -828,7 +1110,13 @@ int board_init(void)
 	setup_soc_rev();
 
 	/* arch id for linux */
+#if defined(CONFIG_MX50_RDP)
 	gd->bd->bi_arch_number = MACH_TYPE_MX50_RDP;
+#elif defined(CONFIG_MX50_ARM2)
+	gd->bd->bi_arch_number = MACH_TYPE_MX50_ARM2;
+#else
+#	error "Unsupported board!"
+#endif
 
 	/* boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
@@ -845,6 +1133,10 @@ int board_init(void)
 	setup_gpmi_nand();
 #endif
 
+#ifdef CONFIG_MXC_EPDC
+	setup_epdc();
+#endif
+
 	return 0;
 }
 
@@ -858,7 +1150,13 @@ int board_late_init(void)
 
 int checkboard(void)
 {
+#if defined(CONFIG_MX50_RDP)
 	printf("Board: MX50 RDP board\n");
+#elif defined(CONFIG_MX50_ARM2)
+	printf("Board: MX50 ARM2 board\n");
+#else
+#	error "Unsupported board!"
+#endif
 
 	printf("Boot Reason: [");