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| author | Helmut Raiger <helmut.raiger@hale.at> | 2011-09-29 05:45:03 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-10-27 21:56:30 +0200 |
| commit | 47c5455a489c8e558ecb002a3a97a030ce490f9e (patch) | |
| tree | a0ecca9a95071e6a963ed4d4abedfa5bf8e7745b /board/freescale/mx31pdk/mx31pdk.c | |
| parent | 43883dc3e50e224ea68031bf34b766544311bf60 (diff) | |
| download | u-boot-imx-47c5455a489c8e558ecb002a3a97a030ce490f9e.zip u-boot-imx-47c5455a489c8e558ecb002a3a97a030ce490f9e.tar.gz u-boot-imx-47c5455a489c8e558ecb002a3a97a030ce490f9e.tar.bz2 | |
mx31: provide readable WEIM CS accessor
setup_weimcs() and some macros are added to support the setup
for i.MX31 WEIM chip selects. As a compromise between verbosity
and readability an ASCII-art'ish bit comment is used instead of
bitfields.
All i.MX31 boards have been patched to use this approach using a
helper program to verify the changes.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/freescale/mx31pdk/mx31pdk.c')
| -rw-r--r-- | board/freescale/mx31pdk/mx31pdk.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 276d451..0e7e0ce 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -28,6 +28,7 @@ #include <netdev.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> #include <watchdog.h> DECLARE_GLOBAL_DATA_PTR; @@ -50,9 +51,16 @@ int dram_init(void) int board_early_init_f(void) { /* CS5: CPLD incl. network controller */ - __REG(CSCR_U(5)) = 0x0000d843; - __REG(CSCR_L(5)) = 0x22252521; - __REG(CSCR_A(5)) = 0x22220a00; + static const struct mxc_weimcs cs5 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(5, &cs5); /* Setup UART1 and SPI2 pins */ mx31_uart1_hw_init(); |