diff options
| author | Helmut Raiger <helmut.raiger@hale.at> | 2011-09-29 05:45:03 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-10-27 21:56:30 +0200 |
| commit | 47c5455a489c8e558ecb002a3a97a030ce490f9e (patch) | |
| tree | a0ecca9a95071e6a963ed4d4abedfa5bf8e7745b /board/freescale/mx31ads/mx31ads.c | |
| parent | 43883dc3e50e224ea68031bf34b766544311bf60 (diff) | |
| download | u-boot-imx-47c5455a489c8e558ecb002a3a97a030ce490f9e.zip u-boot-imx-47c5455a489c8e558ecb002a3a97a030ce490f9e.tar.gz u-boot-imx-47c5455a489c8e558ecb002a3a97a030ce490f9e.tar.bz2 | |
mx31: provide readable WEIM CS accessor
setup_weimcs() and some macros are added to support the setup
for i.MX31 WEIM chip selects. As a compromise between verbosity
and readability an ASCII-art'ish bit comment is used instead of
bitfields.
All i.MX31 boards have been patched to use this approach using a
helper program to verify the changes.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/freescale/mx31ads/mx31ads.c')
| -rw-r--r-- | board/freescale/mx31ads/mx31ads.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/board/freescale/mx31ads/mx31ads.c b/board/freescale/mx31ads/mx31ads.c index 4dd1e63..c668837 100644 --- a/board/freescale/mx31ads/mx31ads.c +++ b/board/freescale/mx31ads/mx31ads.c @@ -25,6 +25,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -48,9 +49,16 @@ int board_early_init_f(void) * the only non-zero field "Wait State Control" is set to half the * default value. */ - __REG(CSCR_U(0)) = 0x00000f00; - __REG(CSCR_L(0)) = 0x10000D03; - __REG(CSCR_A(0)) = 0x00720900; + static const struct mxc_weimcs cs0 = { + /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ + CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0), + /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ + CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), + /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ + CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) + }; + + mxc_setup_weimcs(0, &cs0); /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); |