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authorFabio Estevam <fabio.estevam@freescale.com>2012-10-23 06:34:53 +0000
committerStefano Babic <sbabic@denx.de>2012-10-26 16:28:08 +0200
commite00c89df0605037d417fdb4021d2334bc191beb1 (patch)
treeefb534a620c5c06ac67bb0af323353f0bc4d2693 /board/freescale/mx25pdk
parent787f4f30823a15b1e45c0a0b901cfa5bd415e251 (diff)
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mx25pdk: Add Ethernet support
mx25pdk has a Ethernet port that is connected to its internal FEC controller. In order to power up the Ethernet PHY (DP83640) it is necessary to communicate with the MC34704 PMIC via I2C. Make the FEC ethernet port functional Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'board/freescale/mx25pdk')
-rw-r--r--board/freescale/mx25pdk/mx25pdk.c61
1 files changed, 61 insertions, 0 deletions
diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
index 9bf2d48..72fa6bc 100644
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -26,7 +26,13 @@
#include <asm/arch/clock.h>
#include <mmc.h>
#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <pmic.h>
+#include <fsl_pmic.h>
+#include <mc34704.h>
+#define FEC_RESET_B IMX_GPIO_NR(2, 3)
+#define FEC_ENABLE_B IMX_GPIO_NR(4, 8)
#define CARD_DETECT IMX_GPIO_NR(2, 1)
DECLARE_GLOBAL_DATA_PTR;
@@ -37,6 +43,47 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = {
};
#endif
+static void mx25pdk_fec_init(void)
+{
+ struct iomuxc_mux_ctl *muxctl;
+ struct iomuxc_pad_ctl *padctl;
+ u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5);
+ u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
+
+ /* FEC pin init is generic */
+ mx25_fec_init_pins();
+
+ muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
+ padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
+ /*
+ * Set up FEC_RESET_B and FEC_ENABLE_B
+ *
+ * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12
+ * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17
+ */
+ writel(gpio_mux_mode, &muxctl->pad_d12);
+ writel(gpio_mux_mode, &muxctl->pad_a17);
+
+ writel(0x0, &padctl->pad_d12);
+ writel(0x0, &padctl->pad_a17);
+
+ /* Assert RESET and ENABLE low */
+ gpio_direction_output(FEC_RESET_B, 0);
+ gpio_direction_output(FEC_ENABLE_B, 0);
+
+ udelay(10);
+
+ /* Deassert RESET and ENABLE */
+ gpio_set_value(FEC_RESET_B, 1);
+ gpio_set_value(FEC_ENABLE_B, 1);
+
+ /* Setup I2C pins so that PMIC can turn on PHY supply */
+ writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk);
+ writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat);
+ writel(0x1E8, &padctl->pad_i2c1_clk);
+ writel(0x1E8, &padctl->pad_i2c1_dat);
+}
+
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
@@ -60,6 +107,20 @@ int board_init(void)
return 0;
}
+int board_late_init(void)
+{
+ struct pmic *p;
+
+ mx25pdk_fec_init();
+
+ pmic_init();
+ p = get_pmic();
+ /* Turn on Ethernet PHY supply */
+ pmic_reg_write(p, MC34704_GENERAL2_REG, ONOFFE);
+
+ return 0;
+}
+
#ifdef CONFIG_FSL_ESDHC
int board_mmc_getcd(struct mmc *mmc)
{