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| author | Becky Bruce <becky.bruce@freescale.com> | 2008-11-06 17:36:04 -0600 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2008-11-10 10:10:04 -0600 |
| commit | c759a01a0022de9378a3a761f49786f87684c916 (patch) | |
| tree | be167ba5cd4277aa76faa85a225c20b012137a84 /board/freescale/mpc8641hpcn/law.c | |
| parent | bf9a8c34309ed9276258295db9e9212aabb2531a (diff) | |
| download | u-boot-imx-c759a01a0022de9378a3a761f49786f87684c916.zip u-boot-imx-c759a01a0022de9378a3a761f49786f87684c916.tar.gz u-boot-imx-c759a01a0022de9378a3a761f49786f87684c916.tar.bz2 | |
mpc8641: Change 32-bit memory map
The memory map on the 8641hpcn is modified to look more like
the 85xx boards; this is a step towards a more standardized
layout going forward. As part of this change, we now relocate
the flash.
The regions for some of the mappings were far larger than they
needed to be. I have reduced the mappings to match the
actual sizes supported by the hardware.
In addition I have removed the comments at the head
of the BAT blocks in the config file, rather than updating
them. These get horribly out of date, and it's a simple
matter to look at the defines to see what they are set to
since everything is right here in the same file.
Documentation has been changed to reflect the new map, as this
change is user visible, and affects the OS which runs post-uboot.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Diffstat (limited to 'board/freescale/mpc8641hpcn/law.c')
| -rw-r--r-- | board/freescale/mpc8641hpcn/law.c | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c index 8ec5238..669a091 100644 --- a/board/freescale/mpc8641hpcn/law.c +++ b/board/freescale/mpc8641hpcn/law.c @@ -31,17 +31,20 @@ * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G + * if PCI * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf800_0000 0xf80f_ffff CCSRBAR 1M - * 0xf810_0000 0xf81f_ffff PIXIS 1M - * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * else if RIO + * 0x8000_0000 0x9fff_ffff RapidIO 512M + * endif + * 0xffc0_0000 0xffc0_ffff PCI1 IO 64K + * 0xffc1_0000 0xffc1_ffff PCI2 IO 64K + * 0xffe0_0000 0xffef_ffff CCSRBAR 1M + * 0xffdf_0000 0xffe0_0000 PIXIS, CF 64K + * 0xef80_0000 0xefff_ffff FLASH (boot bank) 8M * * Notes: - * CCSRBAR don't need a configured Local Access Window. + * CCSRBAR doesn't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. */ @@ -52,12 +55,12 @@ struct law_entry law_table[] = { #ifdef CONFIG_PCI SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), - SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_1), + SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI_2), #elif defined(CONFIG_RIO) SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), #endif - SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW(PIXIS_BASE, LAW_SIZE_64K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC), }; |