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authorKumar Gala <galak@kernel.crashing.org>2010-03-26 15:14:43 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-03-30 10:48:30 -0500
commit33f57bd553edf29dffef5a6c7d76e169c79a6049 (patch)
treecae931b06803cf6ff873209a52e5e7dd706beb26 /board/freescale/mpc8610hpcd
parent060f28532b09dd3d2c78423bdd809ac768a27629 (diff)
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85xx: Fix enabling of L1 cache parity on secondary cores
Use the same code between primary and secondary cores to init the L1 cache. We were not enabling cache parity on the secondary cores. Also, reworked the L1 cache init code to match the e500mc L2 init code that first invalidates the cache and locks. Than enables the cache and makes sure its enabled before continuing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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