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| author | York Sun <yorksun@freescale.com> | 2008-05-05 10:19:59 -0500 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-05-21 00:54:36 +0200 |
| commit | 3b80c5f574ad7f6e1c55a68f42752b427fdf778d (patch) | |
| tree | fb2e28d3be49cb3327e7339f4b871864d4755d76 /board/freescale/mpc8610hpcd | |
| parent | 53677ef18e25c97ac613349087c5cb33ae5a2741 (diff) | |
| download | u-boot-imx-3b80c5f574ad7f6e1c55a68f42752b427fdf778d.zip u-boot-imx-3b80c5f574ad7f6e1c55a68f42752b427fdf778d.tar.gz u-boot-imx-3b80c5f574ad7f6e1c55a68f42752b427fdf778d.tar.bz2 | |
Move pixel clock setting to board file
The clock divider has different format in 5121 and 8610. This patch moves it to
board specific code.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/mpc8610hpcd')
| -rw-r--r-- | board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c index b70637f..4db941c 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c @@ -41,6 +41,26 @@ extern unsigned int FSL_Logo_BMP[]; static int xres, yres; +void diu_set_pixel_clock(unsigned int pixclock) +{ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_gur_t *gur = &immap->im_gur; + volatile unsigned int *guts_clkdvdr = &gur->clkdvdr; + unsigned long speed_ccb, temp, pixval; + + speed_ccb = get_bus_freq(0); + temp = 1000000000/pixclock; + temp *= 1000; + pixval = speed_ccb / temp; + debug("DIU pixval = %lu\n", pixval); + + /* Modify PXCLK in GUTS CLKDVDR */ + debug("DIU: Current value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); + temp = *guts_clkdvdr & 0x2000FFFF; + *guts_clkdvdr = temp; /* turn off clock */ + *guts_clkdvdr = temp | 0x80000000 | ((pixval & 0x1F) << 16); + debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); +} void mpc8610hpcd_diu_init(void) { |