powerpc/mpc8xxx: Merge entries in DDR speed table

It is not necessary to keep multiple entries for the same setting in DDR
speed tables. Merge them for smaller tables. Also restructure the tables
for smaller size. Cleanup some typedefs.

Enforce strict checking for speed table. If DIMM is running at higher than
known speed, try to use the highest speed setting. If rank is unknown, it
has to panic.

Removed ODT overriding for P2020DS as it is not necessary.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 102 insertions, 101 deletions

diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index adcbd58..a7ff668 100644
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -11,155 +11,156 @@
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/fsl_ddr_dimm_params.h>
 
-typedef struct {
-	u32 datarate_mhz_low;
-	u32 datarate_mhz_high;
+struct board_specific_parameters {
 	u32 n_ranks;
+	u32 datarate_mhz_high;
 	u32 clk_adjust;
 	u32 cpo;
 	u32 write_data_delay;
 	u32 force_2T;
-} board_specific_parameters_t;
+};
 
 /*
- * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
  *
  * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
  * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
  * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
  * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
  * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
+ *
+ * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
  */
-const board_specific_parameters_t board_specific_parameters_udimm[][20] = {
-	{
+static const struct board_specific_parameters udimm0[] = {
 	/*
-	 *	memory controller 0
-	 *	  lo|  hi|  num|  clk| cpo|wrdata|2T
-	 *	 mhz| mhz|ranks|adjst|    | delay|
+	 * memory controller 0
+	 *   num|  hi|  clk| cpo|wrdata|2T
+	 * ranks| mhz|adjst|    | delay|
 	 */
-		{  0, 333,    2,    8,   7,    5,  0},
-		{334, 400,    2,    8,   9,    5,  0},
-		{401, 549,    2,    8,  11,    5,  0},
-		{550, 680,    2,    8,  10,    5,  0},
-		{681, 850,    2,    8,  12,    5,  1},
-		{  0, 333,    1,    6,   7,    3,  0},
-		{334, 400,    1,    6,   9,    3,  0},
-		{401, 549,    1,    6,  11,    3,  0},
-		{550, 680,    1,    1,  10,    5,  0},
-		{681, 850,    1,    1,  12,    5,  0}
-	},
+	{2,  333,    8,   7,    5,  0},
+	{2,  400,    8,   9,    5,  0},
+	{2,  549,    8,  11,    5,  0},
+	{2,  680,    8,  10,    5,  0},
+	{2,  850,    8,  12,    5,  1},
+	{1,  333,    6,   7,    3,  0},
+	{1,  400,    6,   9,    3,  0},
+	{1,  549,    6,  11,    3,  0},
+	{1,  680,    1,  10,    5,  0},
+	{1,  850,    1,  12,    5,  0},
+	{}
+};
 
-	{
+static const struct board_specific_parameters udimm1[] = {
 	/*
-	 *	memory controller 1
-	 *	  lo|  hi|  num|  clk| cpo|wrdata|2T
-	 *	 mhz| mhz|ranks|adjst|    | delay|
+	 * memory controller 1
+	 *   num|  hi|  clk| cpo|wrdata|2T
+	 * ranks| mhz|adjst|    | delay|
 	 */
-		{  0, 333,    2,     8,  7,    5,  0},
-		{334, 400,    2,     8,  9,    5,  0},
-		{401, 549,    2,     8, 11,    5,  0},
-		{550, 680,    2,     8, 11,    5,  0},
-		{681, 850,    2,     8, 13,    5,  1},
-		{  0, 333,    1,     6,  7,    3,  0},
-		{334, 400,    1,     6,  9,    3,  0},
-		{401, 549,    1,     6, 11,    3,  0},
-		{550, 680,    1,     1, 11,    6,  0},
-		{681, 850,    1,     1, 13,    6,  0}
-	}
+	{2,  333,    8,  7,    5,  0},
+	{2,  400,    8,  9,    5,  0},
+	{2,  549,    8, 11,    5,  0},
+	{2,  680,    8, 11,    5,  0},
+	{2,  850,    8, 13,    5,  1},
+	{1,  333,    6,  7,    3,  0},
+	{1,  400,    6,  9,    3,  0},
+	{1,  549,    6, 11,    3,  0},
+	{1,  680,    1, 11,    6,  0},
+	{1,  850,    1, 13,    6,  0},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+	udimm1,
 };
 
-const board_specific_parameters_t board_specific_parameters_rdimm[][20] = {
-	{
+static const struct board_specific_parameters rdimm0[] = {
 	/*
-	 *	memory controller 0
-	 *	  lo|  hi|  num|  clk| cpo|wrdata|2T
-	 *	 mhz| mhz|ranks|adjst|    | delay|
+	 * memory controller 0
+	 *   num|  hi|  clk| cpo|wrdata|2T
+	 * ranks| mhz|adjst|    | delay|
 	 */
-		{  0, 333,    2,    4,   7,    3,  0},
-		{334, 400,    2,    4,   9,    3,  0},
-		{401, 549,    2,    4,  11,    3,  0},
-		{550, 680,    2,    4,  10,    3,  0},
-		{681, 850,    2,    4,  12,    3,  1},
-	},
+	{2,  333,    4,   7,    3,  0},
+	{2,  400,    4,   9,    3,  0},
+	{2,  549,    4,  11,    3,  0},
+	{2,  680,    4,  10,    3,  0},
+	{2,  850,    4,  12,    3,  1},
+	{}
+};
 
-	{
+static const struct board_specific_parameters rdimm1[] = {
 	/*
-	 *	memory controller 1
-	 *	  lo|  hi|  num|  clk| cpo|wrdata|2T
-	 *	 mhz| mhz|ranks|adjst|    | delay|
+	 * memory controller 1
+	 *   num|  hi|  clk| cpo|wrdata|2T
+	 * ranks| mhz|adjst|    | delay|
 	 */
-		{  0, 333,    2,     4,  7,    3,  0},
-		{334, 400,    2,     4,  9,    3,  0},
-		{401, 549,    2,     4, 11,    3,  0},
-		{550, 680,    2,     4, 11,    3,  0},
-		{681, 850,    2,     4, 13,    3,  1},
-	}
+	{2,  333,     4,  7,    3,  0},
+	{2,  400,     4,  9,    3,  0},
+	{2,  549,     4, 11,    3,  0},
+	{2,  680,     4, 11,    3,  0},
+	{2,  850,     4, 13,    3,  1},
+	{}
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+	rdimm0,
+	rdimm1,
 };
 
 void fsl_ddr_board_options(memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num)
 {
-	const board_specific_parameters_t *pbsp;
-	u32 num_params;
-	u32 i;
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
 	ulong ddr_freq;
 
-	if (!pdimm->n_ranks)
+	if (ctrl_num > 1) {
+		printf("Wrong parameter for controller number %d", ctrl_num);
 		return;
-
-	if (popts->registered_dimm_en) {
-		pbsp = &(board_specific_parameters_rdimm[ctrl_num][0]);
-		num_params = sizeof(board_specific_parameters_rdimm[ctrl_num]) /
-				sizeof(board_specific_parameters_rdimm[0][0]);
-	} else {
-		pbsp = &(board_specific_parameters_udimm[ctrl_num][0]);
-		num_params = sizeof(board_specific_parameters_udimm[ctrl_num]) /
-				sizeof(board_specific_parameters_udimm[0][0]);
 	}
+	if (!pdimm->n_ranks)
+		return;
 
-	/* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
-	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
-	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
-	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
-	 */
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i&1) {	/* odd CS */
-			popts->cs_local_opts[i].odt_rd_cfg = 0;
-			popts->cs_local_opts[i].odt_wr_cfg = 0;
-		} else {	/* even CS */
-			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
-				popts->cs_local_opts[i].odt_rd_cfg = 0;
-				popts->cs_local_opts[i].odt_wr_cfg = 4;
-			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
-			popts->cs_local_opts[i].odt_rd_cfg = 3;
-			popts->cs_local_opts[i].odt_wr_cfg = 3;
-			}
-		}
-	}
+	if (popts->registered_dimm_en)
+		pbsp = rdimms[ctrl_num];
+	else
+		pbsp = udimms[ctrl_num];
 
 	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
 	 * freqency and n_banks specified in board_specific_parameters table.
 	 */
 	ddr_freq = get_ddr_freq(0) / 1000000;
-	for (i = 0; i < num_params; i++) {
-		if (ddr_freq >= pbsp->datarate_mhz_low &&
-		    ddr_freq <= pbsp->datarate_mhz_high &&
-		    pdimm->n_ranks == pbsp->n_ranks) {
-			popts->clk_adjust = pbsp->clk_adjust;
-			popts->cpo_override = pbsp->cpo;
-			popts->write_data_delay = pbsp->write_data_delay;
-			popts->twoT_en = pbsp->force_2T;
-			break;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->cpo_override = pbsp->cpo;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				popts->twoT_en = pbsp->force_2T;
+				goto found;
+			}
+			pbsp_highest = pbsp;
 		}
 		pbsp++;
 	}
 
-	if (i == num_params) {
-		printf("Warning: board specific timing not found "
-			"for data rate %lu MT/s!\n", ddr_freq);
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found "
+			"for data rate %lu MT/s!\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->clk_adjust = pbsp->clk_adjust;
+		popts->cpo_override = pbsp->cpo;
+		popts->write_data_delay = pbsp->write_data_delay;
+		popts->twoT_en = pbsp->force_2T;
+	} else {
+		panic("DIMM is not supported by this board");
 	}
 
+found:
 	/*
 	 * Factors to consider for half-strength driver enable:
 	 *	- number of DIMMs installed