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| author | Dave Liu <daveliu@freescale.com> | 2009-03-27 14:32:43 +0800 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-06-09 22:58:05 +0200 |
| commit | 1b5291dddf5f16c7ae10e3cb165882fa96038b26 (patch) | |
| tree | 7ac021abc9b1e6f08dc64de6128868a28cabd175 /board/freescale/mpc8569mds | |
| parent | f97db54d7e773a32100247ee002686b6a014a87d (diff) | |
| download | u-boot-imx-1b5291dddf5f16c7ae10e3cb165882fa96038b26.zip u-boot-imx-1b5291dddf5f16c7ae10e3cb165882fa96038b26.tar.gz u-boot-imx-1b5291dddf5f16c7ae10e3cb165882fa96038b26.tar.bz2 | |
85xx: Fix the clock adjust of mpc8569mds board
Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Diffstat (limited to 'board/freescale/mpc8569mds')
| -rw-r--r-- | board/freescale/mpc8569mds/ddr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index 4b4533e..e938788 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -54,7 +54,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, * 0110 3/4 cycle late * 0111 7/8 cycle late */ - popts->clk_adjust = 6; + popts->clk_adjust = 4; /* * Factors to consider for CPO: |