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| author | Andy Fleming <afleming@freescale.com> | 2012-10-23 19:03:46 -0500 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-11-27 17:45:17 -0600 |
| commit | e76cd5d4cf311da7d40adc5d6e9b425509cf0205 (patch) | |
| tree | 36c37082482ef310e6419ce57b1b352edccdb29d /board/freescale/mpc8569mds/mpc8569mds.c | |
| parent | 66dc452bfe13b0e276adddf3997b9c5abc00115d (diff) | |
| download | u-boot-imx-e76cd5d4cf311da7d40adc5d6e9b425509cf0205.zip u-boot-imx-e76cd5d4cf311da7d40adc5d6e9b425509cf0205.tar.gz u-boot-imx-e76cd5d4cf311da7d40adc5d6e9b425509cf0205.tar.bz2 | |
8xxx: Change all 8*xx_DDR addresses to 8xxx
There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.
This patch does:
s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g
All 85xx, 86xx, and 83xx have been built with this change.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'board/freescale/mpc8569mds/mpc8569mds.c')
| -rw-r--r-- | board/freescale/mpc8569mds/mpc8569mds.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index d119c65..0d3b418 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -247,7 +247,7 @@ int checkboard (void) #if !defined(CONFIG_SPD_EEPROM) phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; uint d_init; out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); |