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author | Wolfgang Denk <wd@denx.de> | 2009-04-01 22:43:51 +0200 |
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committer | Wolfgang Denk <wd@denx.de> | 2009-04-01 22:43:51 +0200 |
commit | da72af8d727e74093e5fcb3e8599eb8d0df7a749 (patch) | |
tree | 8937781ff72c3841e2352863e3060f0b1a1808ed /board/freescale/mpc8569mds/bcsr.h | |
parent | c2eb8be7f760a2efe30a495bfb10857838dcf3fa (diff) | |
parent | fc39c2fd51e64707de4d61ed49479ebea2847e1b (diff) | |
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'board/freescale/mpc8569mds/bcsr.h')
-rw-r--r-- | board/freescale/mpc8569mds/bcsr.h | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h new file mode 100644 index 0000000..8efe9bd --- /dev/null +++ b/board/freescale/mpc8569mds/bcsr.h @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __BCSR_H_ +#define __BCSR_H_ + +#include <common.h> + +/* BCSR Bit definitions*/ +/****************************************/ +/* BCSR defines */ +/****************************************/ +#define BCSR6_UPC1_EN 0x80 +#define BCSR6_UPC1_POS_EN 0x40 +#define BCSR6_UPC1_ADDR_EN 0x20 +#define BCSR6_UPC1_DEV2 0x10 +#define BCSR6_SD_ENABLE 0x04 +#define BCSR6_TDM2G_EN 0x02 +#define BCSR6_UCC7_RMII_EN 0x01 + +#define BCSR7_UCC1_GETH_EN 0x80 +#define BCSR7_UCC1_RGMII_EN 0x40 +#define BCSR7_UCC1_RTBI_EN 0x20 +#define BCSR7_GETHRST_MRVL 0x04 +#define BCSR7_BRD_WRT_PROTECT 0x02 + +#define BCSR8_UCC2_GETH_EN 0x80 +#define BCSR8_UCC2_RGMII_EN 0x40 +#define BCSR8_UCC2_RTBI_EN 0x20 +#define BCSR8_UEM_MARVEL_RESET 0x02 + +#define BCSR9_UCC3_GETH_EN 0x80 +#define BCSR9_UCC3_RGMII_EN 0x40 +#define BCSR9_UCC3_RTBI_EN 0x20 +#define BCSR9_UCC3_RMII_EN 0x10 +#define BCSR9_UCC3_UEM_MICREL 0x01 + +#define BCSR10_UCC4_GETH_EN 0x80 +#define BCSR10_UCC4_RGMII_EN 0x40 +#define BCSR10_UCC4_RTBI_EN 0x20 + +#define BCSR11_LED0 0x40 +#define BCSR11_LED1 0x20 +#define BCSR11_LED2 0x10 + +#define BCSR12_UCC6_RMII_EN 0x20 +#define BCSR12_UCC8_RMII_EN 0x20 + +#define BCSR15_SMII6_DIS 0x08 +#define BCSR15_SMII8_DIS 0x04 + +#define BCSR16_UPC1_DEV2 0x02 + +#define BCSR17_FLASH_nWP 0x01 + +/*BCSR Utils functions*/ + +void enable_8569mds_flash_write(void); +void disable_8569mds_flash_write(void); +void enable_8569mds_qe_mdio(void); +void disable_8569mds_brd_eeprom_write_protect(void); + +#endif /* __BCSR_H_ */ |