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| author | Anson Huang <b20788@freescale.com> | 2012-12-05 13:58:34 -0500 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2013-03-27 17:43:59 +0800 |
| commit | d26f29ac28fa628c9b0ac87d3cb7576bb0440e50 (patch) | |
| tree | 9bfc1da00558b19216b3bf32ae9ea117d3456f35 /board/freescale/mpc8569mds/bcsr.c | |
| parent | c7c2b8011905d936923be200a5d1b411258f8569 (diff) | |
| download | u-boot-imx-d26f29ac28fa628c9b0ac87d3cb7576bb0440e50.zip u-boot-imx-d26f29ac28fa628c9b0ac87d3cb7576bb0440e50.tar.gz u-boot-imx-d26f29ac28fa628c9b0ac87d3cb7576bb0440e50.tar.bz2 | |
ENGR00235821 mx6: correct work flow of PFDs
PFDs need to be gate/ungate after PLL lock to reset
PFDs to right state. Otherwise PFDs may lose correct
state in state-machine, then no output clock.
For i.MX6DL and i.MX6SL, ROM have taken care of PFD396
already since the bus clock needs it.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'board/freescale/mpc8569mds/bcsr.c')
0 files changed, 0 insertions, 0 deletions