Merge commit 'wd/master'

2 files changed, 45 insertions, 61 deletions

diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S
index 68ccba7..084d4b8 100644
--- a/board/freescale/mpc8544ds/init.S
+++ b/board/freescale/mpc8544ds/init.S
@@ -27,13 +27,6 @@
 #include <config.h>
 #include <mpc85xx.h>
 
-#define LAWAR_TRGT_PCI1		0x00000000
-#define LAWAR_TRGT_PCIE1	0x00200000
-#define LAWAR_TRGT_PCIE2	0x00100000
-#define LAWAR_TRGT_PCIE3	0x00300000
-#define LAWAR_TRGT_LBC		0x00400000
-#define LAWAR_TRGT_DDR		0x00f00000
-
 /*
  * TLB0 and TLB1 Entries
  *
@@ -212,31 +205,31 @@ law_entry:
 	.long (4f-3f)/8
 3:
 	.long	0
-	.long	(LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
+	.long	(LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
 
 	.long	(CFG_PCI1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
 	.long	(CFG_PCI1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
 	.long	(CFG_LBC_CACHE_BASE>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
 
 	.long	(CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
 
 	.long	(CFG_PCIE1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
 	.long	(CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
 	.long	(CFG_PCIE2_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
 
 	/* contains both PCIE3 MEM & IO space */
 	.long	(CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
+	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
 4:
 	entry_end
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index b6c9e93..66cb536 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -29,14 +29,11 @@
 #include <asm/io.h>
 #include <spd.h>
 #include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
 
 #include "../common/pixis.h"
 
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-extern void ft_cpu_setup(void *blob, bd_t *bd);
-#endif
-
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
@@ -52,10 +49,9 @@ int board_early_init_f (void)
 
 int checkboard (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
-	volatile ccsr_lbc_t *lbc = &immap->im_lbc;
-	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
 
 	if ((uint)&gur->porpllsr != 0xe00e0000) {
 		printf("immap size error %x\n",&gur->porpllsr);
@@ -149,8 +145,7 @@ int first_free_busno=0;
 void
 pci_init_board(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 	uint devdisr = gur->devdisr;
 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
@@ -508,51 +503,47 @@ get_board_sys_clk(ulong dummy)
 	return val;
 }
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
+
 void
 ft_board_setup(void *blob, bd_t *bd)
 {
-	u32 *p;
-	int len;
+	int node, tmp[2];
+	const char *path;
 
 	ft_cpu_setup(blob, bd);
 
-	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p != NULL) {
-		*p++ = cpu_to_be32(bd->bi_memstart);
-		*p = cpu_to_be32(bd->bi_memsize);
-	}
+	node = fdt_path_offset(blob, "/aliases");
+	tmp[0] = 0;
+	if (node >= 0) {
 #ifdef CONFIG_PCI1
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
-		debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
-#endif
-#ifdef CONFIG_PCIE1
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
-		debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci0", NULL);
+		if (path) {
+			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
 #ifdef CONFIG_PCIE2
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
-		debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci1", NULL);
+		if (path) {
+			tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
+#endif
+#ifdef CONFIG_PCIE1
+		path = fdt_getprop(blob, node, "pci2", NULL);
+		if (path) {
+			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
 #ifdef CONFIG_PCIE3
-	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
-	if (p != NULL) {
-		p[0] = 0;
-		p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
-		debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
-	}
+		path = fdt_getprop(blob, node, "pci3", NULL);
+		if (path) {
+			tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
+			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+		}
 #endif
+	}
 }
 #endif