Merge with /home/wd/git/u-boot/custodian/u-boot-mpc85xx

1 files changed, 205 insertions, 0 deletions

diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
new file mode 100644
index 0000000..9059934
--- /dev/null
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+#include <miiphy.h>
+
+#include "../common/pixis.h"
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+extern void ft_cpu_setup(void *blob, bd_t *bd);
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+extern long int spd_sdram(void);
+
+void sdram_init(void);
+
+int board_early_init_f (void)
+{
+	return 0;
+}
+
+int checkboard (void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+
+        if ((uint)&gur->porpllsr != 0xe00e0000) {
+		printf("immap size error %x\n",&gur->porpllsr);
+	}
+	printf ("Board: MPC8544DS\n");
+
+	return 0;
+}
+
+long int
+initdram(int board_type)
+{
+	long dram_size = 0;
+
+	puts("Initializing\n");
+
+	dram_size = spd_sdram();
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	/*
+	 * Initialize and enable DDR ECC.
+	 */
+	ddr_enable_ecc(dram_size);
+#endif
+	puts("    DDR: ");
+	return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+	uint *pstart = (uint *) CFG_MEMTEST_START;
+	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *p;
+
+	printf("Testing DRAM from 0x%08x to 0x%08x\n",
+	       CFG_MEMTEST_START,
+	       CFG_MEMTEST_END);
+
+	printf("DRAM test phase 1:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0xaaaaaaaa;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0xaaaaaaaa) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test phase 2:\n");
+	for (p = pstart; p < pend; p++)
+		*p = 0x55555555;
+
+	for (p = pstart; p < pend; p++) {
+		if (*p != 0x55555555) {
+			printf ("DRAM test fails at: %08x\n", (uint) p);
+			return 1;
+		}
+	}
+
+	printf("DRAM test passed.\n");
+	return 0;
+}
+#endif
+
+
+
+int last_stage_init(void)
+{
+	return 0;
+}
+
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+	u8 i, go_bit, rd_clks;
+	ulong val = 0;
+
+	go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
+	go_bit &= 0x01;
+
+	rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+	rd_clks &= 0x1C;
+
+	/*
+	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
+	 * should we be using the AUX register. Remember, we also set the
+	 * GO bit to boot from the alternate bank on the on-board flash
+	 */
+
+	if (go_bit) {
+		if (rd_clks == 0x1c)
+			i = in8(PIXIS_BASE + PIXIS_AUX);
+		else
+			i = in8(PIXIS_BASE + PIXIS_SPD);
+	} else {
+		i = in8(PIXIS_BASE + PIXIS_SPD);
+	}
+
+	i &= 0x07;
+
+	switch (i) {
+	case 0:
+		val = 33333333;
+		break;
+	case 1:
+		val = 40000000;
+		break;
+	case 2:
+		val = 50000000;
+		break;
+	case 3:
+		val = 66666666;
+		break;
+	case 4:
+		val = 83000000;
+		break;
+	case 5:
+		val = 100000000;
+		break;
+	case 6:
+		val = 133333333;
+		break;
+	case 7:
+		val = 166666666;
+		break;
+	}
+
+	return val;
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+        u32 *p;
+        int len;
+
+        ft_cpu_setup(blob, bd);
+
+        p = ft_get_prop(blob, "/memory/reg", &len);
+        if (p != NULL) {
+                *p++ = cpu_to_be32(bd->bi_memstart);
+                *p = cpu_to_be32(bd->bi_memsize);
+        }
+}
+#endif
+