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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-01-16 01:16:16 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-01-16 23:21:55 -0600 |
| commit | 4bcae9c92aee0d72a2f19b81cab27ef38107ce75 (patch) | |
| tree | 774e6717f5bfe8c517b817f3975540e6d5ad2ded /board/freescale/mpc8544ds/init.S | |
| parent | 83d40dfd79fe868796275802f60116d84b9e4395 (diff) | |
| download | u-boot-imx-4bcae9c92aee0d72a2f19b81cab27ef38107ce75.zip u-boot-imx-4bcae9c92aee0d72a2f19b81cab27ef38107ce75.tar.gz u-boot-imx-4bcae9c92aee0d72a2f19b81cab27ef38107ce75.tar.bz2 | |
85xx: convert MPC8544 DS over to use new LAW init code
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/mpc8544ds/init.S')
| -rw-r--r-- | board/freescale/mpc8544ds/init.S | 48 |
1 files changed, 0 insertions, 48 deletions
diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S index 544dc07..3918176 100644 --- a/board/freescale/mpc8544ds/init.S +++ b/board/freescale/mpc8544ds/init.S @@ -172,51 +172,3 @@ tlb1_entry: .long FSL_BOOKE_MAS3(CFG_LBC_NONCACHE_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) 2: entry_end - -/* - * LAW(Local Access Window) configuration: - * - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - * - * LAW 0 is reserved for boot mapping - */ - - .section .bootpg, "ax" - .globl law_entry -law_entry: - entry_start - - .long (4f-3f)/8 -3: - .long 0 - .long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN - - .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M) - - .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K) - - .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M) - - .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M) - - .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K) - - .long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M) - - .long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K) - - /* contains both PCIE3 MEM & IO space */ - .long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff - .long LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M) -4: - entry_end |